Stackable integrated circuit package system
AssigneeSTATS ChipPAC, Ltd.
InventorsSeng Guan Chow, Heap Hoe Kuan, Dioscoro A. Merilo, Antonio B. Dimaano, Jr.
Life of this patent
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Abstract
A stackable integrated circuit package system is provided placing a first integrated circuit die having an interconnect provided thereon in a substrate having a cavity, encapsulating the first integrated circuit die, having the interconnect exposed, in the cavity and along a first side of the substrate, mounting a second integrated circuit die to the first integrated circuit die, and encapsulating the second integrated circuit die along a second side of the substrate.
Claims10
A method of manufacture of a stackable integrated circuit package system comprising:
- providing a substrate having a first side and a second side opposite the first side, the substrate having a cavity provided therein;
- placing a first integrated circuit die in the cavity with a first interconnect extending out from the cavity without connection and a second interconnect connected to the first side;
- encapsulating the first integrated circuit die, the second interconnect, and a portion of the first interconnect in a first encapsulant;
- mounting a second integrated circuit die to the first integrated circuit die with a third interconnect connected to the second side;
- encapsulating the second integrated circuit die and the third interconnect in a second encapsulant;
- and
- mounting external interconnects, not encapsulated by the second encapsulant, to the second side of the substrate.
A method of manufacture of a stackable integrated circuit package system comprising:
- providing a substrate having a first side and a second side opposite the first side, the substrate having a cavity provided therein;
- placing a first integrated circuit die in the cavity with a first interconnect extending out from the cavity without connection;
- electrically connecting the first integrated circuit die and the first side with a second interconnect;
- encapsulating the first integrated circuit die, the second interconnect, and a portion of the first interconnect in a first encapslant;
- mounting a second integrated circuit die to the first integrated circuit die;
- electrically connecting the second integrated circuit die with a third interconnect to the second side;
- encapsulating the second integrated circuit die and the third interconnect in a second encapsulant;
- and
- mounting external interconnects, not encapsulated by the second encapsulant, to the second side.
Dependencies are inferred from the claim text.