US 7,741,695 B2Granted

Semiconductor device

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorKazuhiro Shimizu

Life of this patent

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Abstract

Extending from an upper surface of an n− semiconductor layer on a p− semiconductor substrate to the interface between the n− semiconductor layer and the p− semiconductor substrate, a p+ impurity region is provided. The p+ impurity region defines a high-potential island region, a low-potential island region and a slit region in the n− semiconductor layer. The n− semiconductor layer in the high-potential island region and the n− semiconductor layer in the low-potential island region are connected by the n− semiconductor layer in the slit region, and a logic circuit is formed in the n− semiconductor layer in the high-potential island region. A width in the direction of Y axis of the n− semiconductor layer in the slit region is set to be narrower than a width in the direction of the Y axis of the n− semiconductor layer in the high-potential island region.

Claims14

Dependent claims

A semiconductor device comprising:

a semiconductor substrate of p-type;
a semiconductor layer of n-type formed on said semiconductor substrate;
and
a first impurity region of said p-type formed in said semiconductor layer, extending from an upper surface of said semiconductor layer to an interface between said semiconductor layer and said semiconductor substrate to surround a part of said semiconductor layer, said first impurity region having a higher impurity concentration than said semiconductor layer,
said part of said semiconductor layer including:
a first region sandwiched by said first impurity region so that said first impurity region contacts said first region from both sides of said first region in a first direction parallel to said upper surface of said semiconductor layer,
a second region located apart from said first region and electrically connected to an electrode located directly above said second region, and
a third region located between said first region and said second region to come in contact with said first region and said second region, said third region being sandwiched by said first impurity region so that said first impurity region contacts said third region from both sides of said third region in a second direction parallel to said upper surface of said semiconductor layer and said first direction,
in plan view, said first region, said third region and said second region being arranged along a direction parallel to said upper surface of said semiconductor layer and perpendicular to said first direction and said second direction in this order,
said semiconductor device further comprising:
a first buried impurity region of said n-type formed at an interface between said first region and said semiconductor substrate, said first buried impurity region having a higher impurity concentration than said semiconductor layer;
and
a semiconductor element formed in said semiconductor layer above said first buried impurity region, wherein
a capacity element is electrically connected to said first region, and
in plan view, a width of said third region in said second direction is narrower than a width of said first region in said first direction.

12 more elements

A semiconductor device comprising:

a semiconductor substrate of p-type;
a semiconductor layer of n-type formed on said semiconductor substrate;
a first impurity region of said p-type formed in said semiconductor layer, extending from an upper surface of said semiconductor layer to an interface between said semiconductor layer and said semiconductor substrate, to surround a part of said semiconductor layer, said first impurity region having a higher impurity concentration than said semiconductor layer, said part of said semiconductor layer including:
a first region sandwiched by said first impurity region so that said first impurity region contacts said first region from both sides of said first region in a first direction parallel to said upper surface of said semiconductor layer,
a second region located apart from said first region, and
a third region located between said first region and said second region to come in contact with said first region and said second region, said third region being sandwiched by said first impurity region so that said first impurity region contacts said third region from both sides of said third region in a second direction parallel to said upper surface of said semiconductor layer and said first direction,
in plan view, said first region, said third region and said second region being arranged along a direction parallel to said upper surface of said semiconductor layer and perpendicular to said first direction and said second direction in this order,
said semiconductor device further comprising:
a first buried impurity region of said n-type formed at an interface between said first region and said semiconductor substrate, said first buried impurity region having a higher impurity concentration than said semiconductor layer;
a semiconductor element formed in said semiconductor layer above said first buried impurity region;
a second impurity region of said p-type provided apart from said first impurity region in an upper surface of said second region;
and
a second buried impurity region of said n-type provided at an interface between said second region and said semiconductor substrate directly below said second impurity region, said second buried impurity region having a higher impurity concentration than said semiconductor layer, wherein
a capacity element is electrically connected to said first region;
and
in plan view, a width of said third region in said second direction is narrower than a width of said first region in said first direction.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/919,405Filed 17 Aug 2004
Priority: JP 2004-04100918 Feb 2004
Published: US 2005/0179089 A118 Aug 2005
Granted: 22 Jun 2010
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 84/0188
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their isolation regions
H10D 84/85
Of only insulated-gate FETs [IGFET]: complementary IGFETs, e.g. CMOS
H10W 10/031
Manufacture or treatment: of isolation regions comprising PN junctions