US 7,741,682 B2Granted

Semiconductor integrated circuit device including a silicon layer formed on a diffusion layer

AssigneeElpida Memory, Inc.

InventorMitsunari Sukekawa

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Abstract

A semiconductor integrated circuit device having a pair of adjacent MOS transistors and a contact plug 33, buried into a contact hole formed by a self-aligned contact process using a silicon nitride film as an etching stopper and electrically connected to diffusion layers 2 and 3 constituting the MOS transistor on a silicon substrate 21 surrounded by a device isolation region 4: wherein a silicon layer 28 is formed on the exposed surface of the diffusion layers 2 and 3 by selective epitaxial growth, which is in contact with an end of each gate insulation film 22 on the diffusion layer side; an insulation film 27′ composed of a silicon oxynitride film or a silicon oxide film is buried between the each gate electrode and the silicon layer 28 while being in contact with the gate insulation film 22; and the silicon nitride films 26, 29′, and 32 are isolated from the silicon substrate 21 by the insulation film 27′.

Claims16

Dependent claims

A semiconductor integrated circuit device comprising:

a diffusion region selectively formed in a semiconductor substrate to define a channel region;
a gate electrode structure disposed over the channel region with an intervention of a gate insulating film therebetween, the gate insulating film comprising an extended portion extending from an edge of the gate electrode structure toward the diffusion region;
a silicon layer disposed on the diffusion region and including a contact surface contacting an edge of the extended portion of the gate insulating film;
a first insulating film formed on a substantially entire upper surface of the extended portion of the gate insulating film, the first insulating film having a thickness which is less than a thickness of the silicon layer at the contact surface of the silicon layer;
and
a second insulating film disposed on the first insulating film and elongated over a side surface of the gate electrode structure, the second insulating film being different in material from the first insulating film, and the first insulating film being sandwiched between the second insulating film and the extended portion of the gate insulating film.

3 more elements

A semiconductor device comprising:

a diffusion region formed in a semiconductor substrate to define a channel region;
a gate insulating film formed on the channel region;
a gate electrode structure formed on the gate insulating film and comprising a polysilicon layer formed on the gate insulating film, the gate insulating film comprising an extended portion extending from an edge of the polysilicon film toward the diffusion region;
a first insulating film formed on a substantially entire surface of the extended portion of the gate insulating film and contacting a side surface of the polysilicon layer;
a silicon layer disposed on the diffusion region and including a contact surface contacting an edge of the extended portion of the gate insulating film and a side surface of the first insulating film, the silicon layer having a thickness which is greater than a thickness of the first insulating film at the contact surface of the silicon layer;
and
a second insulating film disposed on the first insulating film and contacting the side surface of the polysilicon layer and elongated over a side surface of the gate electrode structure, the second insulating film being different in material from the first insulating film and being separated from the extended portion of the gate insulating film by the first insulating film.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/520,749Filed 14 Sep 2006
Priority: JP 2005-26872715 Sep 2005
Published: US 2007/0059888 A115 Mar 2007
Granted: 22 Jun 2010
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
H10B 12/485
Data lines or contacts therefor: bit line contacts
H10D 64/0113
To Group IV semiconductors: the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers
H10B 12/488
Data lines or contacts therefor: word lines