US 7,741,676 B2Granted

Semiconductor apparatus and manufacturing method using a gate contact section avoiding an upwardly stepped polysilicon gate contact

AssigneeRicoh Company, Ltd.

InventorYasunori Hashimoto

Life of this patent

Estimating the term…

Loading patent…

Abstract

A semiconductor apparatus includes a cell section including at least two transistors. A layer interval insulation coat is formed at least overlying the gate electrode use polysilicon and the gate contact use polysilicon. A source electrode metal coat is formed overlying the semiconductor substrate and insulated from the gate electrode use polysilicon and the gate contact use polysilicon, and is electrically connected to the body diffusion layer and the source diffusion layer. A gate use connection hole is formed on the layer interval insulation coat overlying the gate contact use polysilicon. The gate use connection hole has a width larger than that of the trench. A gate electrode metal coat is formed on the gate use connection hole and the layer interval insulation coat. The polysilicon coat is formed at the same level or lower than the surface of the semiconductor substrate.

Claims8

Dependent claims

A semiconductor apparatus comprising:

a cell section including at least two transistors, said cell section including:
a drain layer including a semiconductor substrate,
a trench formed on the surface of the semiconductor substrate having a depth reaching the drain layer,
a gate electrode use polysilicon formed in the trench via a gate insulation coat,
a body diffusion layer formed overlying the semiconductor substrate, said body diffusion layer neighboring the trench and shallower than the trench, and
a source diffusion layer formed overlying the semiconductor substrate, said source diffusion layer neighboring the trench and the body diffusion layer and shallower than the body diffusion layer,
a gate contact section including;
a gate contact use concave section formed overlying the semiconductor substrate, said gate contact use concave section being separated from the cell section and formed in succession with the trench and having a larger width than that of the trench, and
a gate contact use polysilicon formed in the gate contact use concave section via an insulation coat and electrically connected to the gate electrode use polysilicon,
a layer interval insulation coat formed at least overlying the gate electrode use polysilicon and the gate contact use polysilicon;
a source electrode metal coat formed overlying the semiconductor substrate, said source electrode metal coat being insulated from the gate electrode use polysilicon and the gate contact use polysilicon, and being electrically connected to the body diffusion layer and the source diffusion layer;
a gate use connection hole formed on the layer interval insulation coat overlying the gate contact use polysilicon, said gate use connection hole having a width larger than that of the trench;
and
a gate electrode metal coat formed on the rate use connection hole and the layer interval insulation coat;
wherein the gate contact use polysilicon is formed one of at the same level with and lower than the surface of the semiconductor substrate, and
wherein the upper surfaces of the gate electrode use polysilicon and the gate contact use polysilicon are lower than the surface of the semiconductor substrate, further comprising a silicon oxide coat formed between the gate contact use polysilicon and the layer interval insulation coat and being separated with an interval from a sidewall of the gate contact use concave section, the upper surface of said silicon oxide coat being the same level with the surface of the semiconductor substrate.

13 more elements

A semiconductor apparatus comprising:

a cell section including at least two transistors, said cell section including:
a drain layer including a semiconductor substrate,
a trench formed on the surface of the semiconductor substrate having a depth reaching the drain layer,
a gate electrode use polysilicon formed in the trench via a gate insulation coat,
a body diffusion layer formed overlying the semiconductor substrate, said body diffusion layer neighboring the trench and shallower than the trench, and
a source diffusion layer formed overlying the semiconductor substrate, said source diffusion layer neighboring the trench and the body diffusion layer and shallower than the body diffusion layer,
a gate contact section including;
a gate contact use concave section formed overlying the semiconductor substrate, said gate contact use concave section being separated from the cell section and formed in succession with the trench and having a larger width than that of the trench, and
a gate contact use polysilicon formed in the gate contact use concave section via an insulation coat and electrically connected to the gate electrode use polysilicon,
a layer interval insulation coat formed at least overlying the gate electrode use polysilicon and the gate contact use polysilicon;
a source electrode metal coat formed overlying the semiconductor substrate, said source electrode metal coat being insulated from the gate electrode use polysilicon and the gate contact use polysilicon, and being electrically connected to the body diffusion layer and the source diffusion layer;
a gate use connection hole formed on the layer interval insulation coat overlying the gate contact use polysilicon, said gate use connection hole having a width larger than that of the trench;
and
a gate electrode metal coat formed on the gate use connection hole and the layer interval insulation coat;
a protection element use concave section formed on the surface of the semiconductor substrate with a larger width than that of the trench;
and
a protection element having a PN diode formed from a protection element use polysilicon, said PN diode being formed in the protection element use concave section via an insulation coat,
wherein the gate contact use polysilicon is formed one of at the same level with and lower than the surface of the semiconductor substrate, and
wherein said layer interval insulation coat is also formed on the protection element use polysilicon, and the protection element use polysilicon is electrically connected between the source electrode metal coat and the gate electrode metal coat.

16 more elements

A semiconductor apparatus comprising:

a cell section including at least two transistors, said cell section including;
a drain layer including a semiconductor substrate,
a trench formed on the surface of the semiconductor substrate having a depth reaching the drain layer,
a gate electrode use polysilicon formed in the trench via a gate insulation coat,
a body diffusion layer formed overlying the semiconductor substrate, said body diffusion layer neighboring the trench and shallower than the trench, and
a source diffusion layer formed overlying the semiconductor substrate, said source diffusion layer neighboring the trench and the body diffusion layer and shallower than the body diffusion layer,
a gate contact section including;
a gate contact use concave section formed overlying the semiconductor substrate, said gate contact use concave section being separated from the cell section and formed in succession with the trench and having a larger width than that of the trench, and
a gate contact use polysilicon formed in the gate contact use concave section via an insulation coat and electrically connected to the gate electrode use polysilicon,
a layer interval insulation coat formed at least overlying the gate electrode use polysilicon and the gate contact use polysilicon;
a source electrode metal coat formed overlying the semiconductor substrate, said source electrode metal coat being insulated from the gate electrode use polysilicon and the gate contact use polysilicon and being electrically connected to the body diffusion layer and the source diffusion layer;
a gate use connection hole formed on the layer interval insulation coat overlying the gate contact use polysilicon, said gate use connection hole having a width larger than that of the trench;
and
a gate electrode metal coat formed on the gate use connection hole and the layer interval insulation coat;
a resistance element use concave section formed on the surface of the semiconductor substrate with a larger width than that of the trench, and
a resistance element use polysilicon arranged in the resistance element use concave section via an insulation coat;
wherein the gate contact use polysilicon is formed one of at the same level with and lower than the surface of the semiconductor substrate, and
wherein said layer interval insulation coat is also formed overlying the resistance element use polysilicon.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/904,917Filed 27 Sep 2007
Priority: JP 2006-26682729 Sep 2006
Published: US 2008/0079081 A13 Apr 2008
Granted: 22 Jun 2010
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

H10D 30/668
Vertical dmos [vdmos] fets: having trench gate electrodes, e.g. UMOS transistors
H10D 12/481
Having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions: having gate…
H10D 30/0295
Of vertical dmos [vdmos] fets: using recessing of the source electrodes
H10D 30/0297
Of vertical dmos [vdmos] fets: using recessing of the gate electrodes, e.g. to form trench gate electrodes