Semiconductor decoupling capacitor
AssigneeBroadcom Corporation
InventorMeng-An Pan
Life of this patent
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Abstract
A semiconductor capacitor that includes a plurality of overlapping conductive layers and a field-effect transistor. The plurality of conductive layers include a first and second conductive layers that are spaced apart to creating a capacitance between the plurality of layers. In the semiconductor capacitor, the FET has a source, a drain and a gate. When the FET is in conduction mode, a capacitance is created between the gate and the conductive path in the semiconductor substrate between the source and the drain. The semiconductor capacitor's total capacitance is increased by coupling the drain and the source to the first conductive layer and coupling the gate to the second conductive layer.
Claims41
A semiconductor capacitor, comprising:
- a first plurality and a second plurality of overlapping metal layers that create a first capacitance between the first and second plurality of metal layers, wherein each layer of the first and second plurality of metal layers includes at least one inter-digital capacitor;
- and
- a field-effect transistor (FET) having a source, a drain, and a gate, wherein a bias of said FET is controlled by biasing said source, drain, and gate with respect to each other;
- wherein a second capacitance is created between the gate and a conductive path between the source and the drain when the FET is in conduction mode;
- and
- wherein the semiconductor capacitor's total capacitance is increased by coupling the drain and the source to the first plurality of metal layers and coupling the gate to the second plurality of metal layers.
A semiconductor capacitor, comprising:
- a first plurality and a second plurality of spaced apart metal layers creating a first capacitance between the first plurality and the second plurality of metal layers;
- and
- a field-effect transistor (FET) comprising:
- a substrate;
- a source formed on the substrate;
- a drain formed on the substrate;
- and
- a gate,
- wherein a bias of said FET is controlled by biasing said source, drain, and gate with respect to each other;
- wherein a second capacitance is created between the gate and a conductive path in the substrate, the conductive path is created by movements of current between the source and the drain when the FET is in conduction, and
- wherein an augmented capacitance is created by combining the first and second capacitances through coupling the drain and the source to the first plurality of metal layers and the gate to the second plurality of metal layers.
A semiconductor capacitor comprising:
- a substrate having first and second capacitor terminals;
- a FET having a source, a drain, and a gate disposed on the substrate, wherein a bias of said FET is controlled by biasing said source, drain, and gate with respect to each other, the FET biased so as to form a conductive channel between the source and the drain, the source and drain are connected to the first capacitor terminal, the gate is connected to the second capacitor terminal;
- and
- a plurality of metal layers, including a first group of metal layers coupled to the first capacitor terminal, and a second group of metal layers coupled to the second capacitor terminal.
Dependencies are inferred from the claim text.