Air gap spacer formation

A transistor device comprising:

• a gate electrode,
• a source/drain contact spaced apart from the gate electrode,
• an inter level dielectric having low step coverage over the gate electrode, the source/drain contact, and partially between the gate electrode and source/drain contact, and
• an air gap, surrounded by the inter level dielectric, between the gate electrode and the source/drain contact.

A method of fabricating a semiconductor device, the method comprising:

• forming a gate electrode and source/drain contact spaced apart from the gate electrode over a substrate;
• forming a sidewall spacer on a side surface of the gate electrode and depositing a layer of dielectric material so that the space between the gate electrode and source/drain contact is occupied by the sidewall spacer and
• dielectric material having combined dielectric constant K1;
• removing the sidewall spacer and dielectric material from between the gate electrode and source/drain contact;
• and
• depositing a dielectric material between the gate electrode and source/drain material and controlling deposition conditions to form an air gap between the gate electrode and source/drain contact such the dielectric material and air gap have a combined dielectric constant K2 less than K1.