Ultra high voltage MOS transistor device
AssigneeUnited Microelectronics Corp.
InventorChing-Hung Kao
Life of this patent
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Abstract
An ultra high voltage MOS transistor device includes a substrate; a source region formed in the substrate; a first doping region formed in the substrate and bordering upon the source region; a first ion well encompassing the source region and the first doping region; a gate oxide layer formed on the source region and on the first ion well; a field oxide layer connected with the gate oxide layer and formed on a semiconductor region; a dielectric layer stacked on the field oxide layer; a drain region formed at one side of the field oxide layer and being spaced apart from the source region; a second ion well encompassing the drain region; and a gate disposed on the gate oxide layer and laterally extending to the field oxide layer and onto the dielectric layer.
Claims18
An ultra high voltage metal-oxide-semiconductor (MOS) transistor device, comprising:
- a substrate of a first conductivity type;
- a source region of a second conductivity type formed in the substrate;
- a first doping region of the first conductivity type formed in the substrate and bordering upon the source region;
- a first ion well of the first conductivity type encompassing the source region and the first doping region;
- a gate oxide layer formed on the source region and on the first ion well;
- a field oxide layer connected with the gate oxide layer and formed on a semiconductor region;
- a dielectric layer stacked on the field oxide layer without connecting with the gate oxide layer, wherein all of the bottom surface of the dielectric layer contacts the field oxide layer;
- a drain region of the second conductivity type formed at one side of the field oxide layer and being spaced apart from the source region;
- a second ion well of the second conductivity type encompassing the drain region;
- and
- a gate disposed on the gate oxide layer and laterally extending to the field oxide layer and onto the dielectric layer.
An ultra high voltage metal-oxide-semiconductor (MOS) transistor device, comprising:
- an epitaxial layer;
- a first ion well of a first conductivity type formed in the epitaxial layer;
- a source region of a second conductivity type formed in the first ion well;
- a first doping region of the first conductivity type formed in the first ion well and bordering upon the source region;
- a gate oxide layer formed on the source region and on the first ion well;
- a second ion well of the second conductivity type formed in the epitaxial layer;
- a drain region of the second conductivity type formed in the second ion well;
- a field oxide layer connected with the gate oxide layer and being formed on the epitaxial layer between the first ion well and the drain region;
- a dielectric layer stacked on the field oxide layer without connecting with the gate oxide layer, wherein all of the bottom surface of the dielectric layer contacts the field oxide layer;
- and
- a gate disposed on the gate oxide layer and laterally extending to the field oxide layer and onto the dielectric layer.
Dependencies are inferred from the claim text.