Self-aligned super stressed PFET
AssigneeInternational Business Machines Corporation
InventorsYaocheng Liu, Zhijiong Luo, Huilong Zhu
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Abstract
The embodiments of the invention comprise a self-aligned super stressed p-type field effect transistor (PFET). More specifically, a field effect transistor comprises a channel region comprising N-doped material and a gate above the channel region. The field effect transistor also includes a source region on a first side of the channel region and a drain region on a second side of the channel region opposite the first side. The source and drain regions each comprise silicon germanium, wherein the silicon germanium has structural indicia of epitaxial growth.
Claims12
A field effect transistor, comprising:
- a channel region;
- a gate above said channel region;
- a source region comprising silicon germanium on a first side of said channel region;
- a drain region comprising silicon germanium on a second side of said channel region opposite said first side,
- wherein said silicon germanium of said source region and of said drain region does not extend beneath said gate;
- and
- a silicon-carbon layer below said channel region, said source region, and said drain region,
- wherein a portion of said silicon-carbon layer below said channel region comprises when viewed in cross-section:
- a horizontal portion,
- a first vertical portion positioned at a first end of said horizontal portion, and
- a second vertical portion positioned at a second end of said horizontal portion opposite said first end of said horizontal portion,
- wherein said first vertical portion and said second vertical portion are positioned below an uppermost surface of said silicon-carbon layer.
A field effect transistor, comprising:
- a channel region;
- a gate above said channel region;
- a source region comprising silicon germanium on a first side of said channel region;
- a drain region comprising silicon germanium on a second side of said channel region opposite said first side,
- wherein said silicon germanium of said source region and of said drain region does not extend beneath said gate;
- and
- a silicon-carbon layer positioned only below said channel region,
- wherein said silicon-carbon layer comprises when viewed in cross-section:
- a horizontal portion,
- a first vertical portion positioned at a first end of said horizontal portion, and
- a second vertical portion positioned at a second end of said horizontal portion opposite said first end of said horizontal portion,
- wherein said first vertical portion and said second vertical portion are positioned below an uppermost surface of said silicon-carbon layer.
A field effect transistor, comprising:
- a channel region;
- a gate above said channel region;
- a source region comprising silicon germanium on a first side of said channel region;
- a drain region comprising silicon germanium on a second side of said channel region opposite said first side;
- and
- a silicon-carbon layer positioned only below said channel region, wherein said silicon-carbon layer comprises when viewed in cross-section:
- a horizontal portion,
- a first vertical portion positioned at a first end of said horizontal portion, and
- a second vertical portion positioned at a second end of said horizontal portion opposite said first end of said horizontal portion,
- wherein said first vertical portion and said second vertical portion are positioned below an uppermost surface of said silicon-carbon layer.
Dependencies are inferred from the claim text.