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US 7,741,630 B2Granted
Resistive memory element and method of fabrication
AssigneeQimonda AG
InventorsKlaus-Dieter Ufert, Josef Willer
Life of this patent
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Abstract
An integrated circuit including a memory cell and a method of manufacturing the integrated circuit are described. The memory cell includes a buried gate select transistor and a resistive memory element coupled to the buried gate select transistor. The resistive memory element stores information based on a resistivity of the resistive memory element.
Claims14
An integrated circuit, comprising:
- a buried gate select transistor comprising a source region and a drain region;
- and
- a resistive memory element coupled to the buried gate select transistor, the resistive memory element storing information based on a resistivity of the resistive memory element, the resistive memory element comprising a stack of a plurality of layers, the stack comprising a bottom contact layer, a switching layer disposed above the bottom contact layer and a top contact layer disposed above the switching layer;
- a common line;
- wherein the drain region of the buried gate select transistor is in direct physical contact to the bottom contact layer of the stack of the resistive memory element;
- and
- wherein the source region of the buried gate select transistor is in direct physical contact to the common line wherein the buried gate select transistor comprises:
- a recess formed in an active area of a substrate, the active area comprising a source region and a drain region, the recess located between the source region and the drain region;
- a gate oxide layer lining the recess;
- and a gate comprising a conductive material at least partially filling the recess.
7 more elements
A method of manufacturing an integrated circuit, the method comprising:
- forming a buried gate select transistor comprising a source region and a drain region;
- and
- forming a resistive memory element coupled to the buried gate transistor, the resistive memory element storing information based on a resistivity of the resistive memory element, the resistive memory element comprising a stack of a plurality of layers, the stack comprising a bottom contact layer, a switching layer disposed above the bottom contact layer and a top contact layer disposed above the switching layer
- directly contacting the drain region of the buried gate select transistor to the bottom contact layer, and
- forming a common line such that it is in direct physical contact to the source region of the buried gate select transistor wherein the buried gate select transistor comprises:
- a recess formed in an active area of a substrate, the active area comprising a source region and a drain region, the recess located between the source region and the drain region;
- a gate oxide layer lining the recess;
- and a gate comprising a conductive material at least partially filling the recess.
5 more elements
An integrated circuit comprising:
- a buried gate select transistor, the buried gate select transistor comprising a trench formed in a substrate, a gate oxide layer lining the trench, a gate at least partially filling the trench, a source region and a drain region;
- and
- a resistive memory element disposed above the buried gate select transistor, the resistive memory element comprising a stack of a plurality of layers, the stack comprising a bottom contact layer, a switching layer disposed above the bottom contact layer and a top contact layer disposed above the switching layer;
- a common line;
- wherein the drain region of the buried gate select transistor is in direct physical contact to the bottom contact layer of the stack of the resistive memory element;
- and
- wherein the source region of the buried gate select transistor is in direct physical contact to the common line.
4 more elements
A memory module comprising:
- a plurality of integrated circuits that are electrically coupled to one another, wherein the integrated circuits each comprise a memory cell comprising a buried gate select transistor comprising a source region and a drain region and a resistive memory element coupled to the buried gate select transistor, the resistive memory element storing information based on a resistivity of the resistive memory element, the resistive memory element comprising a stack of a plurality of layers, the stack comprising a bottom contact layer, a switching layer disposed above the bottom contact layer and a top contact layer disposed above the switching layer;
- a common line;
- wherein the drain region of the buried gate select transistor is in direct physical contact to the bottom contact layer of the stack of the resistive memory element;
- and
- wherein the source region of the buried gate select transistor is in direct physical contact to the common line wherein the buried gate select transistor comprises:
- a recess formed in an active area of a substrate, the active area comprising the source region and the drain region, the recess located between the source region and the drain region;
- a gate oxide layer lining the recess;
- and a gate comprising a conductive material at least partially filling the recess.
5 more elements
Dependencies are inferred from the claim text.