Method for fabricating a probing pad of an integrated circuit chip
AssigneeUnited Microelectronics Corp.
InventorChien-Ming Lan
Life of this patent
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Abstract
A method for fabricating a probing pad is disclosed. A substrate having thereon a dielectric layer is provided. An inlaid metal wiring is formed in the dielectric layer. The inlaid metal wiring and the dielectric layer are covered with a passivation dielectric film. A portion of the passivation dielectric film is then etched away to form a reinforcement pattern on the inlaid metal wiring. The reinforcement pattern has inter-space that exposes a portion of the underlying inlaid metal wiring. A conductive pad is formed over the reinforcement pattern and the passivation dielectric film. The conductive pad fills the inter-space of the reinforcement pattern.
Claims22
A method for fabricating a probing pad of an integrated circuit chip, comprising the steps of:
- providing a substrate having thereon a dielectric layer;
- forming an inlaid metal wiring in the dielectric layer, wherein the inlaid metal wiring has an exposed top surface;
- covering the top surface of the inlaid metal wiring and the dielectric layer with a passivation dielectric film;
- etching away a portion of the passivation dielectric film to form a reinforcement pattern on the inlaid metal wiring, wherein the reinforcement pattern has inter-space that exposes a portion of the underlying inlaid metal wiring;
- and
- forming a conductive pad over the reinforcement pattern and the passivation dielectric film, wherein the conductive pad fills the inter-space of the reinforcement pattern.
A method of probing an integrated circuit chip, comprising:
- providing an integrated circuit chip comprising a substrate having thereon a dielectric layer;
- an inlaid metal wiring in the dielectric layer, wherein the inlaid metal wiring has an exposed top surface;
- a passivation dielectric film covering perimeter of the inlaid metal wiring;
- a reinforcement pattern directly on the inlaid metal wiring, wherein the reinforcement pattern has inter-space that exposes a portion of the underlying inlaid metal wiring;
- a conductive pad over the reinforcement pattern and the passivation dielectric film, wherein the conductive pad fills the inter-space of the reinforcement pattern;
- and
- performing a probing test by depressing a probe tip on the conductive pad, wherein the probe tip produces a stress that is counteracted by the reinforcement pattern, thereby avoiding exposure of the inlaid metal wiring.
Dependencies are inferred from the claim text.