Semiconductor wafer with improved crack protection
AssigneeFreescale Semiconductor, Inc.
InventorsHeng Keong Yip, Wai Yew Lo, Lan Chu Tan
Life of this patent
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Abstract
A method of manufacturing a semiconductor wafer for dicing includes providing a semiconductor wafer including a substrate and a plurality of upper layers on the substrate that form a formation of die areas. The formation is arranged so that adjacent die areas are separated by a path for a dicing tool. Within each path, a pair of spaced apart lines is fabricated. Each line defines a dicing edge of a respective path and has at least one trench extending between a top surface of the wafer and the substrate. Each trench is filled with a stress absorbing material for reducing die tool induced stress on the die areas during dicing.
Claims15
A method of manufacturing a semiconductor wafer for dicing, the method comprising:
- providing the semiconductor wafer including a substrate having a plurality of upper layers and a plurality of die areas, wherein adjacent die areas are separated by a path for a dicing tool;
- fabricating, within each path, a pair of spaced apart lines, each of the spaced apart lines defines a dicing edge of the path and comprises a plurality of trenches having ends, wherein the trenches are arranged end to end such that apexes of longitudinally aligned trenches point towards each other, and wherein a horizontal cross-section of each end of consecutive trenches has an acuate shape that promotes propagation of cracks therebetween during dicing, and wherein each trench extends between a top surface of the semiconductor wafer and the substrate;
- and
- filling each trench with a stress absorbing material for reducing die tool induced stress on the die areas during dicing.
A semiconductor wafer, comprising:
- a substrate;
- a plurality of upper layers and a plurality of die areas formed on the substrate, wherein adjacent die areas are separated by a path for a dicing tool;
- a pair of spaced apart lines within each path, each line of the pair defining a dicing edge of the path and comprising a plurality of trenches that extend between a top surface of the wafer and the substrate, and wherein the trenches have ends, and the trenches are arranged end to end, each end having a horizontal cross-section that has an acuate shape that promotes cracking propagation therebetween during dicing and wherein apexes of the acuate ends of consecutive trenches point at each other;
- and
- a polymeric stress absorbing material disposed within each trench for reducing die tool induced stress on the plurality of die areas during dicing.
A semiconductor wafer, comprising:
- a substrate;
- a plurality of upper layers and a plurality of die areas formed on the substrate, wherein the die areas are separated from each other by intersecting horizontal and vertical paths;
- a pair of spaced apart lines within each horizontal and vertical path, each line of the pair defining a dicing edge of the path, wherein each line comprises a plurality of trenches that have ends, wherein the trenches extend between a top surface of the wafer and the substrate of the wafer, wherein the plurality of trenches of each line have a finite length and are arranged end-to-end, and wherein an area of each path between adjacent intersections along the path includes more than one trench of the plurality of trenches for each line and wherein the ends of consecutive trenches have a horizontal cross-section with an acuate shape that promotes cracking propagation between the consecutive end-to-end trenches during dicing;
- and
- a polymeric stress absorbing material disposed within each trench.
Dependencies are inferred from the claim text.