US 7,741,193 B2 · SOI structure having a SiGe layer interposed between the silicon and the insulator

Abstract

A semiconductor structure and a method of manufacturing a silicon on insulator (SOI) structure having a silicon germanium (SiGe) layer interposed between the silicon and the insulator. According to one manufacturing method, a first SiGe layer, a silicon layer, and a second SiGe layer are epitaxially grown in sequence over a first substrate, and then an insulating layer is formed on the second SiGe layer. Then, impurity ions are implanted into a predetermined location of the first substrate underlying the first SiGe layer to form an impurity implantation region. A second substrate is bonded to the insulating layer on the first substrate. After the first substrate is separated along the impurity implantation region and removed, the first SiGe layer remaining on the surface of the separated region is removed so that the surface of the silicon layer may be exposed.

Claims7

Dependent claims

A method of manufacturing a silicon on insulator (SOI) wafer having a silicon germanium (SiGe) layer thereon, comprising:

forming a porous silicon layer on a first substrate;
epitaxially growing 1) a silicon layer directly on the porous silicon layer and 2) the SiGe layer directly on the silicon layer in sequence, the SiGe layer having Ge atomic ratio of 0.19 to 0.2;
forming an insulating layer on the SiGe layer;
bonding a second substrate to the insulating layer on the first substrate to form a bonded first and second substrate;
first annealing the bonded first and second substrate at a temperature of about 1,180° C.;
separating the first substrate from the bonded first and second substrate along the porous silicon layer and removing the first substrate after the first annealing;
and
removing remnants of the porous silicon layer remaining on the second substrate so as to expose the silicon layer on the second substrate.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

11/270,508Filed 10 Nov 2005 · division

Priority

30 Jan 2002

Published

US 2006/0063356 A123 Mar 2006

Granted

22 Jun 2010

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10D 30/0323
Comprising silicon, e.g. amorphous silicon or polysilicon: comprising monocrystalline silicon
H10D 30/6748
Group IV materials, e.g. germanium or silicon carbide: having a multilayer structure or superlattice structure
H10P 90/1908
Preparing SOI wafers: using silicon implanted buried insulating layers, e.g. oxide layers [SIMOX]
H10P 90/1916
Using bonding: with separation or delamination along an ion implanted layer, e.g. Smart-cut

Family

Application60/352,260Us provisional application · filed 30 Jan 2002

Application10/354,197Parent of this continuation · filed 30 Jan 2003

Application11/150,292Parent of this division · filed 13 Jun 2005

US 2006/0063356 A1Pre-grant publication · published 23 Mar 2006

US 7,180,138 B2Parent of this division

Application11/150,292Parent of this continuation

US 2003/0230778 A1Published application

US 2005/0242396 A1Published application

US 7,741,193 B2This patent

From the US filing history. Foreign family members aren’t listed.

SOI structure having a SiGe layer interposed between the silicon and the insulator

Life of this patent

SOI structure having a SiGe layer interposed between the silicon and the insulator

Life of this patent

Abstract

Claims7