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US 7,741,185 B2Granted
Method of manufacturing semiconductor device
AssigneeFujitsu Semiconductor Limited
InventorRyo Tanabe
Life of this patent
Estimating the term…
Abstract
Each of channel regions 2a and 3b is covered by a gate electrode 6 via a gate insulation film 5 and side wall spacers 9 from its top face to both side faces along an x-direction. In other words, there is no insulation material of an STI element isolation structure 4 on both side faces along the x-direction of each of the channel regions 2b and 3b (in a non-contact state), thereby preventing stress in a z-direction from being applied by the STI element isolation structure 4 to each of the channel region 2b and 3b.
Claims5
A method of manufacturing a semiconductor device, comprising the steps of:
- forming a groove within an element isolation region of a semiconductor substrate;
- embedding an insulation material in the groove to form an element isolation structure to thereby define an active region on the semiconductor substrate;
- partially removing the insulation material of the element isolation structure to expose a surface layer portion of the active region;
- introducing an element into a surface of the element isolation structure;
- pattern-forming a gate electrode in such a manner as to cover the surface layer portion from a top face to both side faces thereof via a gate insulation film;
- introducing impurities into the active region on both sides of the gate electrode to form a pair of impurity diffused layers;
- and
- performing annealing processing to activate the impurities and relieve compression stress of the element isolation structure.
5 more elements
Dependencies are inferred from the claim text.