Method for fabricating SOI device
AssigneeAdvanced Micro Devices, Inc.
InventorMario M. Pelella
Life of this patent
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Abstract
A method is provided for fabricating a semiconductor on insulator (SOI) device. The method includes, in one embodiment, providing a monocrystalline silicon substrate having a monocrystalline silicon layer overlying a monocrystalline silicon substrate and separated therefrom by a dielectric layer. A well region is ion implanted in the monocrystalline silicon substrate. A gate electrode material is deposited overlying the monocrystalline silicon layer. The gate electrode material is photolithographically patterned and etched using a minimum lithography feature size to form a first gate electrode, a second gate electrode and a spacer having the minimum lithography feature size. The gate electrode material is then isotropically etched to reduce the width of the first gate electrode, the second gate electrode and the spacer.
Claims20
A method for fabricating a semiconductor on insulator (SOI) device having a monocrystalline silicon layer overlying a monocrystalline silicon substrate and separated therefrom by a dielectric layer, the method comprising the steps of:
- ion implanting a well region in the monocrystalline silicon substrate;
- then depositing a gate electrode material overlying the monocrystalline silicon layer;
- photolithographically patterning and etching the gate electrode material using a minimum lithography feature size to form a first gate electrode, a second gate electrode and a spacer having the minimum lithography feature size;
- and
- then isotropically etching the gate electrode material to reduce the width of the first gate electrode, the second gate electrode and the spacer.
A method for fabricating a semiconductor on insulator (SOI) device having a monocrystalline silicon layer overlying a monocrystalline silicon substrate and separated therefrom by a dielectric layer, the method comprising the steps of:
- forming a dielectric isolation region extending through the monocrystalline silicon layer to the dielectric layer;
- ion implanting a well region in the monocrystalline silicon substrate;
- depositing a layer of gate electrode material overlying the monocrystalline silicon layer and the dielectric isolation region;
- patterning the layer of gate electrode material to simultaneously form a gate electrode overlying the monocrystalline silicon layer and a spacer overlying the dielectric isolation region, wherein the gate electrode and the spacer each have a minimum width;
- and
- etching the dielectric isolation region and the dielectric layer using the spacer as an etch mask.
A method for fabricating a semiconductor on insulator (SOI) device having a monocrystalline silicon layer overlying a monocrystalline silicon substrate and separated therefrom by a dielectric layer, the method comprising the steps of:
- forming a dielectric isolation region extending through the monocrystalline silicon layer to the dielectric layer;
- ion implanting a well region in the monocrystalline silicon substrate;
- depositing a gate electrode layer overlying the monocrystalline silicon layer and the dielectric isolation region;
- patterning the gate electrode layer using a photolithographic patterning and etching process to form a P-channel gate electrode and an N-channel gate electrode overlying the monocrystalline silicon layer and a spacer overlying the dielectric isolation region, wherein the P-channel gate electrode, the N-channel gate electrode, and the spacer each have a minimum photolithographic feature size;
- and
- subsequently isotropically etching the spacer to reduce the minimum photolithographic feature size.
Dependencies are inferred from the claim text.