Variable strength ECC

A non-volatile memory device comprising:

• a non-volatile memory array containing a plurality of non-volatile memory cells arranged in a plurality of sectors, each sector having an associated ECC code, wherein a data size of the associated ECC code is selectable from two or more differing numbers of ECC code symbols;
• wherein the non-volatile memory device is adapted to error check a selected sector read from the non-volatile memory array utilizing the selected number of ECC code symbols contained in the associated ECC code utilizing the associated ECC code;
• and
• wherein the non-volatile memory device is adapted to select the data size of an associated ECC code based on a bit error rate and/or use level of the sector having the associated ECC code or based on one of a data type and a memory device type while a data size of the sector having the associated ECC code stays the same.

A non-volatile memory device comprising:

• a non-volatile memory array containing a plurality of non-volatile memory cells arranged in a plurality of sectors, each sector having an associated ECC code, wherein a data size of the associated ECC code is selectable from two or more differing numbers of ECC code symbols;
• wherein the non-volatile memory device is adapted to error check a selected sector read from the non-volatile memory array utilizing the selected number of ECC code symbols contained in the associated ECC code utilizing the associated ECC code;
• wherein the non-volatile memory device is adapted to change the data size of the associated ECC codes of one or more sectors of a memory area of the non-volatile array when a bit error rate of a memory area increases or decreases;
• and
• wherein the non-volatile memory device is adapted to change the data size of the associated ECC codes of one or more sectors of a memory area of the non-volatile array for an increase or decrease in one of an instantaneous bit error rate for a memory area, an average bit error rate as indicated by a running average of a number of errors seen for each read operation on a memory area, and an incidence rate of uncorrectable errors for a memory area.

A memory controller comprising:

• a host interface;
• a memory device interface for one or more memory devices, wherein at least one of the one or more memory devices has a memory array containing a plurality of memory cells arranged in a plurality of sectors, each sector having an associated ECC code, where a data size of the associated ECC code is selectable;
• a data buffer coupled to the memory device interface;
• a host transfer circuit coupled to the data buffer and to the host interface;
• and
• an ECC generator/checker circuit, wherein the data buffer and the ECC generator/checker circuit are coupled to receive a read sector and where the ECC generator/checker circuit is adapted to error check the read sector utilizing an ECC error decoder configuration selectable in response to the data size of the associated ECC code of the read sector;
• wherein the memory controller is adapted to select the data size of an associated ECC code based on a bit error rate and/or use level of the sector having the associated ECC code or based on one of a data type and a memory device type while a data size of the sector having the associated ECC code stays the same.

A system comprising:

• a host coupled to a memory system, wherein the memory system comprises,
• one or more memory devices, wherein the one or more memory devices each contain a memory array with a plurality of memory cells arranged in a plurality of sectors, each sector of the plurality of sectors having an associated ECC code, and where a data size of the associated ECC code is selected from two or more differing numbers of ECC check bytes;
• and
• wherein the system is adapted to error check a selected sector read from the one or more memory devices utilizing the selected number of ECC check bytes contained in the associated ECC code;
• and
• wherein the system is adapted to select the data size of an associated ECC code based on a bit error rate and/or use level of the sector having the associated ECC code or based on one of a data type and a memory device type while a data size of the sector having the associated ECC code stays the same.

A memory module, comprising:

• at least one memory device;
• a housing enclosing the at least one memory device;
• and
• a plurality of contacts configured to provide selective contact between the at least one memory device and a host system;
• wherein the at least one memory device contains a memory array containing a plurality of memory cells arranged in a plurality of sectors, each sector of the plurality of sectors having an associated ECC code stored in a spare area of the memory array, and where a data size of the associated ECC code is selectable from two or more differing numbers of ECC symbols;
• wherein the memory module is adapted to error check a selected sector read from the at least one memory device utilizing the selected number of ECC symbols contained in the associated ECC code;
• and
• wherein the memory module is adapted to select the data size of an associated ECC code based on a bit error rate and/or use level of the sector having the associated ECC code or based on one of a data type and a memory device type while a data size of the sector having the associated ECC code stays the same.

A memory module, comprising:

• a plurality of contacts;
• and
• two or more memory devices, each having access lines selectively coupled to the plurality of contacts;
• wherein at least one of the memory devices comprises:
• a memory array containing a plurality of memory cells arranged in a plurality of sectors, each sector of the plurality of sectors having an associated ECC code, and where a data size of the associated ECC code is selectable from two or more differing numbers of ECC check bytes;
• and
• wherein the memory module is adapted to error check a selected sector read from the at least one memory device utilizing the selected number of ECC check bytes contained in the associated ECC code;
• and
• wherein the memory module is adapted to select the data size of an associated ECC code based on a bit error rate and/or use level of the sector having the associated ECC code or based on one of a data type and a memory device type while a data size of the sector having the associated ECC code stays the same.

A method of operating a memory system comprising:

• reading an ECC data block having a plurality of bytes from a selected memory device of one or more memory devices, wherein the ECC data block contains an associated ECC code, and where a size of the associated ECC code is selectable from two or more differing numbers of ECC code symbols;
• while a data size of the read ECC data block stays the same, selecting a number of ECC code symbols from the two or more differing numbers of ECC code symbols based on a bit error rate and/or a use level of the read ECC data block or based on one of a memory device type and a data type;
• and
• error checking the read ECC data block by evaluating the read ECC data block with the selected number of ECC code symbols contained in the associated ECC code.

A method of operating a memory device comprising:

• reading a sector of a plurality of sectors from a memory array, wherein each sector has an associated ECC check byte code, and where a data size of the associated ECC check byte code is selectable from two or more differing numbers of ECC code symbols;
• and
• error checking the sector by selecting an appropriate ECC check byte code data size while a data size of the read sector stays the same and evaluating the sector and the associated ECC check byte code in an ECC check for the ECC check byte code data size,
• wherein the selection of the appropriate ECC check byte code data size is based on a bit error rate and/or a use level of the read sector or based on one of a data type and a memory array type.

A method of operating a memory controller comprising:

• receiving sector and ECC code pair of a plurality of sectors and ECC code pairs read from a selected memory device of one or more memory devices, wherein a data size of the ECC code is selectable from two or more differing numbers of ECC code symbols;
• and
• error checking the received sector by selecting an appropriate ECC code size while a data size of the sector stays the same and evaluating the sector and ECC code pair in an ECC error check;
• wherein the selection of the appropriate ECC code size is based on a bit error rate and/or a use level of the received sector or based on one of a data type and a memory array type.

A method of correcting errors in a read data segment comprising:

• reading an ECC data block of at least one memory device and an associated ECC code, wherein a data size of the associated ECC code is selectable from two or more differing numbers of ECC code symbols;
• while a data size of the ECC data block stays the same, selecting a number of ECC code symbols from the two or more differing numbers of ECC code symbols based on a bit error rate and/or a use level of the ECC data block or based on one of a memory device type and a data type;
• and
• error checking the ECC data block by evaluating the ECC data block with the selected number of ECC code symbols in an ECC error check.

A machine-usable medium, the machine-usable medium containing a software routine for causing a processor to execute a method, wherein the method comprises:

• reading an ECC data block and an associated ECC code, wherein a data size of the associated ECC code is selectable from two or more differing numbers of ECC code symbols;
• while a data size of the ECC data block stays the same, selecting a number of ECC code symbols from the two or more differing numbers of ECC code symbols based on a bit error rate and/or a use level of the ECC data block or based on one of a memory device type and a data type;
• and
• error checking the ECC data block by evaluating the ECC data block with the selected number of ECC code symbols contained in the associated ECC code in an ECC error check.