Arrangement comprising a first semiconductor chip and a second semiconductor chip connected thereto

An arrangement comprising

• a first semiconductor chip and a second semiconductor chip connected thereto,
• where the second semiconductor chip is additionally connected to electrical loads and drives these electrical loads on the basis of a timing which is defined by load control data,
• where the first semiconductor chip transmits via a transmission channel to the second semiconductor chip the load control data and pilot data which control the second semiconductor chip,
• where the transmission channel comprises:
• a first transmission clock line via which the first semiconductor chip transmits a transmission clock signal to the second semiconductor chip;
• a second transmission clock line via which the first semiconductor chip transmits an inverse of the transmission clock signal to the second semiconductor chip;
• a first data line via which the first semiconductor chip transmits the load control data and the pilot data to the second semiconductor chip in time with the transmission clock signal;
• a second data line via which the first semiconductor chip transmits an inverse of the load control data and an inverse of the pilot data to the second semiconductor chip;
• and
• a chip select line via which the first semiconductor chip transmits a chip select signal to the second semiconductor chip,
• wherein said chip select signal signals to the second semiconductor chip a start and end of transmission of data intended for the second semiconductor chip via the data line,
• where the second semiconductor chip transmits to the first semiconductor chip diagnostic data which represent at least one of states prevailing in the second semiconductor chip and events which occur in the second semiconductor chip,
• wherein the first semiconductor chip includes means for transmitting appropriate pilot data to the second semiconductor chip, and the second semiconductor chip includes means for controlling a transmission rate by which the diagnostic data is transmitted to the first semiconductor chip in accordance with the appropriate pilot data.