Feed forward equalizer for a communication system

A system, comprising:

• a communications medium;
• a transceiver to connect to said communications medium, said transceiver to include a feed-forward equalizer to receive an input data signal and output an equalized signal, said feed-forward equalizer to comprise:
• a tapped filter having multiple filter multipliers and a summing element;
• a correlator having multiple correlator multipliers, with each correlator multiplier having a corresponding integrator;
• a set of shared delay elements to connect to said filter multipliers and said correlator multipliers, with each delay element to include multiple delay stages, with a first delay stage to receive an input data signal and output a first delay signal to one of said correlator multipliers and none of said filter multipliers, and a second delay stage to receive said first delay signal and output a second delay signal to one of said filter multipliers and none of said correlator multipliers;
• and
• an error signal generator to connect to said correlator, said error signal generator comprising a slicer and a subtraction node, said slicer to receive as input a linear input signal from said summing element and output a sliced signal, the subtraction node to subtract said sliced signal from said linear input signal to form an error signal for output to said correlator.

A feed forward equalizer, comprising:

• a filter having multiple filter multipliers and a summing element;
• a correlator having multiple correlator multipliers, with each correlator multiplier having a corresponding integrator, each integrator comprises a linear stage and a set of three current mirrors to connect to said linear stage;
• a set of shared delay elements to connect to said filter multipliers and said correlator multipliers, with each delay element to include multiple delay stages, with a first delay stage to receive an input data signal and output a first delay signal to only one of said correlator multipliers and a second delay stage, and a second delay stage to receive said first delay signal and output a second delay signal to only one of said filter multipliers and another delay element;
• and
• an error signal generator to connect to said correlator, said error signal generator comprising a slicer and a subtraction node, said slicer to receive as input a linear input signal from said summing element and output a sliced signal, the subtraction node to subtract said sliced signal from said linear input signal to form an error signal for output to said correlator.