System and apparatus for using test structures inside of a chip during the fabrication of the chip

A method for evaluating a fabrication of a semiconductor wafer, the method comprising:

• identifying a location on a die of the wafer for each of a plurality of test structures;
• when the wafer is in a partially fabricated form, generating a corresponding signal from each of the plurality of test structures by directing energy onto the individual test structures using a contactless medium;
• measuring electrical or optical activity from at least some of the plurality of test structures on which the corresponding signal is generated;
• correlating the measured electrical or optical activity for individual test structures to a corresponding performance parameter;
• performing analysis using the performance parameter of each of the individual test structures in order to evaluate performance of one or more fabrication steps in the fabrication of the wafer.