Mask network design for scan-based integrated circuits

A computer-readable memory having computer-readable program code embodied therein for causing a computer system to perform a method for synthesizing an output-mask controller for generating a plurality of output-mask enable signals for selectively masking off unknown (‘x’) captured scan data in first selected scan cells from propagating through scan chains for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit in a selected scan-test mode or a selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, a plurality of pattern generators, a plurality of pattern compactors, and an output-mask network embedded on the scan data input path of second selected scan cells, each scan chain comprising multiple scan cells coupled in series;

• said method comprising computer-implemented steps of:
• (a) compiling HDL (hardware description language) code modeled at RTL (register-transfer level) or at gate-level that represents said scan-based integrated circuit into a design database;
• (b) specifying input constraints on said output-mask controller;
• (c) synthesizing said output-mask controller and said output-mask network on said design database according to said input constraints;
• and
• (d) generating synthesized HDL code for said output-mask controller and said output-mask network in a selected RTL or gate-level format.

An electronic design automation system comprising:

• a processor;
• a bus coupled to said processor;
• and a computer-readable
• memory coupled to said bus and having computer-readable program code embodied therein for causing said electronic design automation system to perform a method for synthesizing an output-mask controller for generating a plurality of output-mask enable signals for selectively masking off unknown (‘x’) captured scan data in first selected scan cells from propagating through scan chains for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit in a selected scan-test mode or a selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, a plurality of pattern generators, a plurality of pattern compactors, and an output-mask network embedded on a scan data input path of second selected scan cells, each scan chain comprising multiple scan cells coupled in series;
• said method comprising computer-implemented steps of:
• (a) compiling HDL (hardware description language) code modeled at RTL (register-transfer level) or at gate-level that represents said scan-based integrated circuit into a design database;
• (b) specifying input constraints on said output-mask controller;
• (c) synthesizing said output-mask controller and said output-mask network on said design database according to said input constraints;
• and
• (d) generating synthesized HDL code for said output-mask controller and said output-mask network in a selected RTL or gate-level format.

A method for synthesizing a set/reset controller for generating a plurality of set/reset signals for selectively masking off unknown (‘x’) captured scan data in first selected scan cells from propagating through scan chains for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit in a selected scan-test mode or a selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, a plurality of pattern generators, and a plurality of pattern compactors, each scan chain comprising multiple scan cells coupled in series, said plurality of set/reset signals controlling selected set/reset inputs of second selected scan cells;

• said method comprising computer-implemented steps of:
• (a) a computer compiling HDL (hardware description language) code modeled at RTL (register-transfer level) or at gate-level that represents said scan-based integrated circuit into a design database;
• (b) specifying input constraints on said set/reset controller;
• (c) synthesizing said set/reset controller on said design database according to said input constraints;
• and
• (d) generating synthesized HDL code for said set/reset controller in a selected RTL or gate-level format.

A computer-readable memory having computer-readable program code embodied therein for causing a computer system to perform a method for synthesizing a set/reset controller for generating a plurality of set/reset signals for selectively masking off unknown (‘x’) captured scan data in first selected scan cells from propagating through scan chains for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit in a selected scan-test mode or a selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, a plurality of pattern generators, and a plurality of pattern compactors, each scan chain comprising multiple scan cells coupled in series, said plurality of set/reset signals controlling selected set/reset inputs of second selected scan cells;

• said method comprising computer-implemented steps of:
• (a) compiling HDL (hardware description language) code modeled at RTL (register-transfer level) or at gate-level that represents said scan-based integrated circuit into a design database;
• (b) specifying input constraints on said set/reset controller;
• (c) synthesizing said set/reset controller on said design database according to said input constraints;
• and
• (d) generating synthesized HDL code for said set/reset controller in a selected RTL or gate-level format.

An electronic design automation system comprising:

• a processor;
• a bus coupled to said processor;
• and a computer-readable memory coupled to said bus and having computer-readable program code embodied therein for causing said electronic design automation system to perform a method for synthesizing a set/reset controller for generating a plurality of set/reset signals for selectively masking off unknown (‘x’) captured scan data in first selected scan cells from propagating through scan chains for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit in a selected scan-test mode or a selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, a plurality of pattern generators, and a plurality of pattern compactors, each scan chain comprising multiple scan cells coupled in series, said plurality of set/reset signals controlling selected set/reset inputs of second selected scan cells;
• said method comprising computer-implemented steps of:
• (a) compiling HDL (hardware description language) code modeled at RTL (register-transfer level) or at gate-level that represents said scan-based integrated circuit into a design database;
• (b) specifying input constraints on said set/reset controller;
• (c) synthesizing said set/reset controller on said design database according to said input constraints;
• and
• (d) generating synthesized HDL code for said set/reset controller in a selected RTL or gate-level format.