US 7,735,048 B1 · Achieving fast parasitic closure in a radio frequency integrated circuit synthesis flow

Abstract

Methods achieve fast parasitic closure in IC (integrated circuit) synthesis flow with particular application to RFIC (radio frequency integrated circuit) synthesis flow. Parasitic corners generated based on earlier layout statistics are incorporated into circuit resizing to enable parasitic robust designs. The worst-case parasitic corners are generated efficiently without expensive statistical computations. A performance-driven placement with simultaneous fast rough routing and device tuning generates high quality placements and compensates for layout induced performance degradations. A regression-tree based macromodeling methodology is introduced for modeling of electrical performances to enable true performance-driven layout synthesis. To improve sampling quality, an annealing-based placer can be used to perform sampling. The modeling methodology can be adapted to include automatically adjusting the device tuning ranges to meet certain model accuracy requirements.

Claims31

Dependent claims

A method for synthesizing an IC (integrated circuit), comprising:

determining a first layout for the IC, the first layout including a first specification of device parameters, placement, and routing, wherein determining the first layout includes determining parasitic statistical data from the first layout;
and
determining a second layout for the IC, the second layout including a second specification of device parameters, placement, and routing, wherein determining the second layout includes:
using a computer for determining a plurality of first-layout parasitic corners from the parasitic statistical data of the first layout, the first-layout parasitic corners characterizing worst-case samples for a plurality of performance models for the IC;
determining the device parameters for the second layout by using the first-layout parasitic corners to resize the device parameters of the first layout;
and
determining the placement and the routing for the second layout after determining the device parameters for the second layout.

4 more elements

An apparatus for synthesizing an IC (integrated circuit), the apparatus comprising a computer for executing computer instructions, wherein the computer includes computer instructions for:

determining a first layout for the IC, the first layout including a first specification of device parameters, placement, and routing, wherein determining the first layout includes determining parasitic statistical data from the first layout;
and
determining a second layout for the IC, the second layout including a second specification of device parameters, placement, and routing, wherein determining the second layout includes:
determining a plurality of first-layout parasitic corners from the parasitic statistical data of the first layout, the first-layout parasitic corners characterizing worst-case samples for a plurality of performance models for the IC;
determining the device parameters for the second layout by using the first-layout parasitic corners to resize the device parameters of the first layout;
and
determining the placement and the routing for the second layout after determining the device parameters for the second layout.

4 more elements

A computer-readable medium that stores instructions that when executed by a computer implement a method for synthesizing an IC (integrated circuit), the method comprising:

determining a first layout for the IC, the first layout including a first specification of device parameters, placement, and routing, wherein determining the first layout includes determining parasitic statistical data from the first layout;
and
determining a second layout for the IC, the second layout including a second specification of device parameters, placement, and routing, wherein determining the second layout includes:
determining a plurality of first-layout parasitic corners from the parasitic statistical data of the first layout, the first-layout parasitic corners characterizing worst-case samples for a plurality of performance models for the IC;
determining the device parameters for the second layout by using the first-layout parasitic corners to resize the device parameters of the first layout;
and
determining the placement and the routing for the second layout after determining the device parameters for the second layout.

4 more elements

Dependencies are inferred from the claim text.

Achieving fast parasitic closure in a radio frequency integrated circuit synthesis flow

Life of this patent

Achieving fast parasitic closure in a radio frequency integrated circuit synthesis flow

Life of this patent

Abstract

Claims31