Wiring layout apparatus, wiring layout method, and wiring layout program for semiconductor integrated circuit

Wiring layout method for a semiconductor integrated circuit, the method being realized by a computer including a layout design unit, a critical wiring detection unit, a rewiring unit and a strip-conductor-size variation determination unit, the method comprising:

• designing a wiring layout for a semiconductor integrated circuit, by the layout design unit;
• analyzing a delay of signal propagation in the wiring layout so as to detect wiring strip conductors that configure a signal path whose timing is critical, by the critical wiring detection unit;
• determining, with regard to the wiring layout, the uniformity of a wiring pattern of an area in the vicinity of the critical wiring strip conductor, based on a filling rate of the wiring strip conductors in the area in the vicinity of the critical wiring strip conductor and the number of the vertexes, of end portions of the wiring strip conductors, which exist in the area in the vicinity of the critical wiring strip conductor, and when it is determined that the wiring pattern is non-uniform, rearranging, so as to improve the uniformity of the wiring pattern, the wiring strip conductors by performing at least one of the following operations:
• removing the wiring strip conductor laid in the area in the vicinity of the critical wiring strip conductor and laying the wiring strip conductor in another area;
• removing the wiring strip conductor laid in another area and laying the wiring strip conductor in the area in the vicinity of the critical wiring strip conductor;
• interchanging the wiring strip conductor laid in the area in the vicinity of the critical wiring strip conductor and the wiring strip conductor laid in another area;
• and extending the wiring strip conductor laid in the area in the vicinity of the critical wiring strip conductor, by the rewiring unit;
• and
• determining and evaluating the uniformity of the pattern of the rearranged wiring layout based on the filling rate of the wiring strip conductors in the area in the vicinity of the critical wiring strip conductor and the number of the vertexes, of the end portions of the wiring strip conductors, which exist in the area in the vicinity of the critical wiring strip conductor, so as to determine whether or not variation in the size of the critical wiring strip conductor falls within a tolerance range, by the strip-conductor-size variation determination unit.

A computer-readable medium including a wiring layout program for a semiconductor integrated circuit, the program comprising:

• a critical wiring detection procedure of analyzing a delay of signal propagation in the wiring layout based on the result of wiring layout for a semiconductor integrated circuit so as to detect wiring strip conductors that configure a signal path whose timing is critical;
• and
• a rewiring procedure including a procedure of evaluating, with regard to the wiring layout, the uniformity of a wiring pattern based on a filling rate of the wiring strip conductors in the area in the vicinity of the critical wiring strip conductor and the number of the vertexes, of end portions of the wiring strip conductors, which exist in the area in the vicinity of the critical wiring strip conductor and performing rewiring so as to improve the uniformity of the wiring pattern, and a wiring optimizing procedure of performing rewiring by at least one of moving, or by interchanging, or extending the wiring strip conductors,
• and causing the computer to execute these series of procedures.