Method and system for creating a boolean model of multi-path and multi-strength signals for verification
AssigneeCadence Design Systems, Inc.
InventorsKei-Yong Khoo, Mitchell Hines, Chih-Chang Lin
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Abstract
A system, method, computer program product for verification and equivalence checking. In one approach, the system, method, and computer program product analyzes the switching paths in a manner consistent with circuit functionality to provide a complete application which can verify the complex characteristics in the circuits to the accurate RTL model function, including FPGA, ROM Arrays, RAM circuits, and other custom integrated circuit designs.
Claims23
A computer implemented method for performing verification of an integrated circuit, comprising:
- using a computer system which comprises at least one processor and is programmed for:
- reading a design description of the integrated circuit;
- replacing a multi-strength device in the design description with a replacement logic which accurately models the multi-strength device and comprises one or more encoded output signals, wherein
- at least one of the output signals is determined by comparing a first individual binary signal of a first input signal with a second individual binary signal of a second input signal, in which three or more individual binary signals are used to model multi-strength behavior of at least one of the first input signal and the second input signal, and
- the one or more encoded output signals model and present multiple strength behavior of the multi-strength device as a plurality of Boolean logic values;
- performing the verification by evaluating the design description together with the logic of the integrated circuit using a verification logic, wherein
- the verification logic comprises a process that does not consider strength information of the integrated circuit;
- and
- displaying the design description with the logic on a display apparatus or storing the design description with the logic in a computer readable storage medium or a storage device of the computer system.
A system for performing verification of an integrated circuit, comprising:
- a computer system which comprises at least one processor and is programmed for:
- reading a design description of the integrated circuit;
- replacing a multi-strength device in the design description with a replacement logic which accurately models the multi-strength device and comprises one or more encoded output signals, wherein
- at least one of the output signals is determined by comparing a first individual binary signal of a first input signal with a second individual binary signal of a second input signal, in which three or more individual binary signals are used to model multi-strength behavior of at least one of the first input signal and the second input signal, and
- the one or more encoded output signals model and present multiple strength behavior of the multi-strength device as a plurality of Boolean logic values;
- and
- performing the verification by evaluating the design description together with the logic of the integrated circuit using a verification simulator, wherein
- the verification simulator comprises a means for verification that does not consider strength information of the integrated circuit;
- and
- displaying the design description with the logic on a display apparatus or storing the design description with the logic in a computer readable storage medium or a storage device of the computer system.
A computer program product comprising computer usable storage medium having executable coded which, when executed by at least one processor of a computer system, causes the computer system to perform a process for verification of an integrated circuit, the process comprising:
- reading a design description of the integrated circuit;
- replacing a multi-strength device in the design description with a replacement logic which accurately models the multi-strength device and comprises one or more encoded output signals, wherein
- at least one of the output signals is determined by comparing a first individual binary signal of a first input signal with a second individual binary signal of a second input signal, in which three or more individual binary signals are used to model multi-strength behavior of at least one of the first input signal and the second input signal, and
- the one or more encoded output signals model and present multiple strength behavior of the multi-strength device as a plurality of Boolean logic values;
- performing the verification by evaluating the design description together with the logic of the integrated circuit using a verification simulator, wherein
- the verification logic comprises a process that does not consider strength information of the integrated circuit;
- and
- displaying the design description with the logic on a display apparatus or storing the design description with the logic in a computer readable storage medium or a storage device of the computer system.
Dependencies are inferred from the claim text.