Path memory circuit

A path memory circuit for use in a Viterbi decoding process performed based on state transitions through a number n (n is a positive integer) of states, comprising M (M is a positive integer) stages of storage circuits, each storage circuit including n rows of selective storage circuits, each selective storage circuit including a selection circuit for selectively outputting an input according to a result of the Viterbi decoding and a storage element circuit for storing a result selectively outputted from the selection circuit, the path memory circuit comprising:

• a memory area A formed by the storage circuits of the first to ith (i is an integer from 0 to M) stages;
• a memory area B formed by the selective storage circuits that select and hold a decoding result for any state k (k is an integer from 1 to n) of the storage circuits from the i+1th stage to the Mth stage;
• and
• a memory area C formed by the selective storage circuits other than the memory area A and the memory area B,
• wherein according to a memory length control signal, the storage circuits of the j (j is an integer from i+1 to M)th and subsequent stages in the memory area C are stopped, and the selection circuits of the jth and subsequent stages in the memory area B select an output of the selective storage circuits of a preceding storage circuit belonging to the memory area B.