Signal decoder, a signal decoding method and a storage system
AssigneeRohm Co., Ltd.
InventorsAtsushi Esumi, Hidemichi Mizuno
Life of this patent
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Abstract
An LDPC iteration decoder includes a second interleaver for performing interleave processing on a signal series outputted from a soft output detection unit, an LDPC decoder for implementing LDPC decoding processing on a signal that has undergone interleave processing; a checking unit for checking that an error has been corrected by the LDPC decoder; a second de-interleaver for performing sort processing the reverse of the second interleaver on a signal that has been LDPC decoded; a judging unit for judging whether to carry out iteration processing again; and a DAE for computing a likelihood again, in cases in which iteration decoding is carried out, and giving feedback to the front stage of the second interleaver.
Claims5
A signal decoder comprising:
- an interleaving circuit for sorting an order of an input signal series of a prescribed number of signals;
- a low density parity check decoder for performing low density parity check decoding, using a prescribed matrix, on the signal series sorted by the interleaving circuit;
- and
- a de-interleaving circuit for sorting an order of signals outputted from the low density parity check decoder;
- wherein
- the prescribed matrix is a matrix for checking a low density parity series, and a logical sum of elements of M columns, M being an integer greater than or equal to 2, included in the matrix gives a zero matrix;
- wherein the interleaving circuit sorts at least one signal, by interchanging with another signal, among the signals acted upon relating to respective columns, with the logical sum of the M columns, M being an integer greater than or equal to 2, being a zero matrix, by the low density parity check decoder.
A storage system, having a signal storage system comprising a write channel for writing data to a storage device, and a read channel for reading data stored in the storage device, wherein
- the write channel comprises:
- a first encoder for run-length encoding of data;
- a second encoder for encoding data encoded by the first encoder, using a low density parity check code;
- and
- a writing unit for writing the data encoded by the second encoder, to the storage device;
- and
- the read channel comprises:
- a soft output detection unit for calculating likelihood for data read from the storage unit and outputting a soft decision value;
- a first decoder, corresponding to the second encoder, for decoding data outputted from the soft output detection unit;
- and
- a second decoder, corresponding to the first encoder, for decoding the data decoded by the first decoder;
- and
- the first decoder comprises:
- an interleaving circuit for sorting an order of the data outputted from the soft output detection unit;
- a low density parity check decoder for performing low density parity check decoding on a signal series sorted by the interleaving circuit;
- and
- a de-interleaving circuit for sorting an order of a signal outputted from the low density parity check decoder;
- wherein
- a rule for sorting in the interleaving circuit is decided based on an error generation model for the data outputted from the soft output detection unit.
A signal decoding method comprising:
- sorting an order of an input signal series of a prescribed number of signals with an interleaving circuit;
- performing low density parity check decoding with a low density parity check decoder, using a prescribed matrix, on the signal series;
- and
- sorting an order of signals outputted from the low density parity check decoding step with a de-interleaving circuit;
- wherein
- the prescribed matrix is a matrix for checking a low density parity series, and a logical sum of elements of M columns, M being an integer greater than or equal to 2, included in the matrix gives a zero matrix;
- wherein the interleaving circuit sorts at least one signal, by interchanging with another signal, among the signals acted upon relating to respective columns, with the logical sum of the M columns, M being an integer greater than or equal to 2, being a zero matrix, by the low density parity check decoder.
Dependencies are inferred from the claim text.