Mitigating silent data corruption in a buffered memory module architecture

A system comprising:

• a buffered memory module to store data and allow read and write access;
• a buffered memory module channel coupled to the memory module to receive data from the buffered memory module;
• a memory device coupled with the buffered memory module channel to receive data from the buffered memory module;
• a memory channel bit-lane error detector coupled with the buffered memory module channel, to apply an error detection code to the received data on each bit-lane of the buffered memory module channel, and to detect an error on a bit-lane, the memory channel bit-lane error detector having an M-bit Cyclic redundancy check (CRC) component and an N-bit CRC component, wherein the N-bit CRC component is to be selected if at least one bit-lane of the buffered memory module channel fails, and wherein the buffered memory module channel includes at least one additional bit-lane to convey CRC information without having to append CRC characters to the data;
• a memory content error detector coupled with the buffered memory module channel, the memory content error detector to receive data from the memory module, to detect errors in the received data, to correct errors in the received data if the error is correctable and if the bit-lane error detector indicates that there is no error on a bit-lane, and to indicate whether data received from the buffered memory module channel contains a correctable error;
• and
• a retry engine coupled with the memory content error detector, the retry engine capable of signaling a data retry if at least one bit-lane of the buffered memory module channel fails and the memory content error detector indicates a correctable error.

An apparatus comprising:

• means for receiving data from a memory module through bit-lanes of a memory module data channel, the means for receiving data having an M-bit cyclic redundancy check (CRC) component and an N-bit CRC component, wherein the N-bit CRC component is to be selected if at least one bit-lane of the buffered memory module channel fails, and wherein the buffered memory module channel includes at least one additional bit-lane to convey CRC information without having to append CRC characters to the data;
• means for applying an error detection code to the received data on each bit-lane to detect an error on a bit-lane;
• means for detecting errors in the received data and for correcting errors in the received data if the means for detecting determines that the error is correctable and if the means for applying indicates that there is no error on a bit-lane;
• and
• means for causing the means for receiving to retry receiving the data on the bit-lanes if the bit-lane error detector indicates an error on a bit-lane.