US 7,734,975 B2Granted

Semiconductor integrated circuit having built-n self test circuit of logic circuit and embedded device, and design apparatus thereof

AssigneeKabushiki Kaisha Toshiba

InventorsKenichi Anzou, Chikako Tokunaga, Tetsu Hasegawa

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Abstract

A semiconductor integrated circuit contains a logic circuit which operates upon receiving a clock; a logic built-in self test circuit which executes a built-in self test of said logic circuit, said logic built-in self test circuit having a pattern generator which generates a pattern to be input to said logic circuit, a pattern compactor which receives data output from said logic circuit that has received the pattern, compacts the data, and outputs a result, and a logic built-in self test control unit which controls operations of said pattern generator and said pattern compactor and controls an operation of causing a scan path in said logic circuit to shift upon receiving the pattern; a device circuit which operates upon receiving the clock; and a device circuit built-in self test circuit which executes a built-in self test of said device circuit.

Claims16

Dependent claims

A semiconductor integrated circuit comprising:

a logic circuit which operates upon receiving a clock;
a logic built-in self test circuit which executes a built-in self test of said logic circuit, said logic built-in self test circuit having a pattern generator which generates a pattern to be input to said logic circuit, a pattern compactor which receives data output from said logic circuit that has received the pattern, compacts the data, and outputs a result, and a logic built-in self test control unit which controls operations of said pattern generator and said pattern compactor and controls an operation of causing a scan path in said logic circuit to shift upon receiving the pattern;
a device circuit which operates upon receiving the clock;
and
a device circuit built-in self test circuit which executes a built-in self test of said device circuit,
wherein while said device circuit built-in self test circuit is executing the built-in self test of said device circuit, said logic built-in self test circuit is set in a low power consumption mode, said pattern generator maintains a data holding state immediately before said logic built-in self test circuit is set in the low power consumption mode, generates a fixed value in place of the pattern, and inputs the fixed value to said logic circuit, and said pattern compactor maintains a data holding state immediately before said logic built-in self test circuit is set in the low power consumption mode and stops a compaction operation.

3 more elements

A semiconductor integrated circuit design apparatus comprising:

a memory built-in self test circuit generation device which generates circuit information of a built-in self test circuit of a memory included in a semiconductor integrated circuit on the basis of configuration information of the memory;
a logic built-in self test circuit generation device which generates circuit information of a built-in self test circuit of a logic circuit included in the semiconductor integrated circuit on the basis of information of the logic circuit;
a test sequence control circuit generation device which generates circuit information of a test sequence control circuit that controls a test sequence so as to satisfy a power consumption condition, on the basis of the circuit information of the memory built-in self test circuit, the circuit information of the logic circuit built-in self test circuit, a test condition of the semiconductor integrated circuit, and the power consumption condition in a test;
and
a test circuit insertion device which receives the circuit information of the semiconductor integrated circuit and adds the circuit information of the memory built-in self test circuit, the circuit information of the logic circuit built-in self test circuit, and the circuit information of the test sequence control circuit to the circuit information of the semiconductor integrated circuit, thereby outputting circuit information of the semiconductor integrated circuit in which the memory built-in self test circuit, the logic circuit built-in self test circuit, and the test sequence control circuit are inserted.

2 more elements

Dependencies are inferred from the claim text.