Serial scan chain control within an integrated circuit
AssigneeArm Limited
InventorsRobert Campbell Aitken, Dipesh Ishwerbhai Patel, Gary Robert Waggoner
Life of this patent
Estimating the term…
Abstract
An integrated circuit 2 includes a plurality of circuit blocks 38, 40, 44 each having an associated serial scan chain loop 32, 34, 36 which extends from a converter 10, to the circuit block 38, 42, 44 in question and then back to the converter 10. Multiplexing circuitry 50, 52 associated with each serial scan chain loop 32, 34, 36 is used to either include that serial scan chain loop 32, 34, 36 in a combined serial scan chain or to bypass that serial scan chain loop 32, 34, 36. The circuit blocks 38, 42, 44 may be bypassed in this way if they are defective or if they are powered-down.
Claims13
An integrated circuit comprising:
- a plurality of circuit blocks;
- a test controller responsive to test commands received from outside said integrated circuit to perform test operations upon said plurality of circuit blocks;
- a plurality of serial scan chain loops, each one of said plurality of serial scan chain loops extending from said test controller to a respective one of said plurality of circuit blocks to communicate test signals therewith and back to said test controller, wherein said test controller comprises multiplexing circuitry coupled to said plurality of serial scan chain loops and responsive to configuration commands to link together selected serial scan chain loops of said plurality of serial scan chain loops to form a combined serial scan chain loop having an input connection and an output connection such that test signals can be serially scanned through said combined serial scan chain loop to provide communication of said test signals between a test device external of said integrated circuit and those of said plurality of circuit blocks corresponding to said selected serial scan chain loops;
- and
- a power controller coupled to at least some of said plurality of circuit blocks and responsive to power commands to selectively place one or more of said plurality of circuit blocks in a power saving state in which test signals cannot be communicated.
An integrated circuit comprising:
- a plurality of circuit block means;
- test controller means, responsive to test commands received from outside said integrated circuit, for performing test operations upon said plurality of circuit block means;
- a plurality of serial scan chain loop means, each one of said plurality of serial scan chain loop means extending from said test controller means to a respective one of said plurality of circuit block means to communicate test signals therewith and back to said test controller means, wherein said test controller means comprises multiplexing means coupled to said plurality of serial scan chain loops and responsive to configuration commands for linking together selected serial scan chain loop means of said plurality of serial scan chain loop means to form a combined serial scan chain loop means having an input connection and an output connection such that test signals can be serially scanned through said combined serial scan chain loop means to provide communication of said test signals between a test device external of said integrated circuit and those of said plurality of circuit block means corresponding to said selected serial scan chain loop means;
- and
- power control means, coupled to at least some of said plurality of circuit block means and responsive to power commands, for selectively placing one or more of said plurality of circuit blocks in a power saving state in which test signals cannot be communicated.
A method of testing an integrated circuit comprising a plurality of circuit blocks, a test controller responsive to test commands received from outside said integrated circuit to perform test operations upon said plurality of circuit blocks and a plurality of serial scan chain loops, each one of said plurality of serial scan chain loops extending from said test controller to a respective one of said plurality of circuit blocks to communicate test signals therewith and back to said test controller, said method comprising the steps of:
- linking, in response to a configuration command to said test controller, together selected serial scan chain loops of said plurality of serial scan chain loops to form a combined serial scan chain loop having an input connection and an output connection;
- and
- serially scanning test signals through said combined serial scan chain loop to provide communication of said test signals between a test device external of said integrated circuit and those of said plurality of circuit blocks corresponding to said selected serial scan chain loops, wherein, in response to a power command, a power controller coupled to at least some of said plurality of circuit blocks selectively places one or more of said plurality of circuit blocks in a power saving state in which test signals cannot be communicated.
Dependencies are inferred from the claim text.