US 7,734,968 B2Granted

Mechanism to provide test access to third-party macro circuits embedded in an ASIC (application-specific integrated circuit)

AssigneeInternational Business Machines Corporation

InventorsRichard J. Grupp, Kelly A. Ockunzzi, Mark R. Taylor

Life of this patent

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Abstract

Novel structures and testing methods for the FPGAs (Field-Programmable Gate Arrays) embedded in an ASIC (Application-Specific Integrated Circuits). Basically, a shift/interface system is coupled between the FPGAs and the ASIC. During normal operation, the shift/interface system electrically couples the FPGAs to the ASIC. During the testing of the FPGAs, the shift/interface system scans in FPGA test data in series, then feeds the FPGA test data to the FPGAs, then receives FPGA response data from the FPGAs, and then scans out the FPGA response data in series. During the testing of the ASIC, the shift/interface system scans in ASIC test data in series, then feeds the ASIC test data to the ASIC, then receives ASIC response data from the ASIC, and then scans out the ASIC response data in series.

Claims15

Dependent claims

A digital system, comprising:

(a) N macro circuits, N being a positive integer;
(b) an application-specific integrated circuit (ASIC);
and
(c) a shift/interface system being coupled to the N macro circuits and the ASIC,
wherein, in response to the N macro circuits and the ASIC being in normal operation, the shift/interface system is configured to electrically couple each macro circuit of the N macro circuits to the ASIC,
wherein, in response to the N macro circuits being tested, the shift/interface system is further configured to electrically disconnect each macro circuit of the N macro circuits from the ASIC, to receive macro circuit test data in series, then to feed the macro circuit test data to the N macro circuits, then to receive macro circuit response data from the N macro circuits, and then to scan-out the macro circuit response data in series, and
wherein, in response to the ASIC being tested, the shift/interface system is further configured to electrically disconnect each macro circuit of the N macro circuits from the ASIC, to receive ASIC test data in series, then to feed the ASIC test data to the ASIC, then to receive ASIC response data from the ASIC, and then to scan-out the ASIC response data in series.

4 more elements

A system testing and operating method, comprising the steps of:

(a) providing a digital system including (i) N macro circuits, (ii) an application-specific integrated circuit (ASIC), and (iii) a shift/interface system being coupled to the N macro circuits and the ASIC;
(b) in response to the N macro circuits and the ASIC being in normal operation, using the shift/interface system to electrically couple each macro circuit of the N macro circuits to the ASIC;
(c) in response to the N macro circuits being tested, electrically disconnecting each macro circuit of the N macro circuits from the ASIC, (i) scanning-in macro circuit test data in series into the shift/interface system, (ii) feeding the macro circuit test data from the shift/interface system to the N macro circuits, (iii) using the shift/interface system to receive macro circuit response data from the N macro circuits, and (iv) scanning-out the macro circuit response data in series from the shift/interface system;
and
(d) in response to the ASIC being tested, electrically disconnecting each macro circuit of the N macro circuits from the ASIC, (i) scanning-in ASIC test data in series into the shift/interface system, (ii) feeding the ASIC test data from the shift/interface system to the ASIC, (iii) using the shift/interface system to receive ASIC response data from the ASIC, and (iv) scanning-out the ASIC response data in series from the shift/interface system.

2 more elements

A system testing method, comprising the steps of:

(a) providing a digital system including
(i) a macro circuit,
(ii) an application-specific integrated circuit (ASIC), and
(iii) a shift/interface system being coupled to the macro circuit and the ASIC, and
(iv) a multiple-input signature register (MISR) including K MISR stages, K being a positive integer of at least 2, the K MISR stages being coupled together in a chain, being coupled to K output pins of the macro circuit, and being coupled to K shift/interface circuits of the shift/interface system, wherein the K shift/interface circuits are coupled together in a chain;
(b) scanning-in macro circuit test data in series into the shift/interface system;
(c) transmitting the macro circuit test data from the shift/interface system to the macro circuit in parallel;
(d) using the macro circuit to process the macro circuit test data into macro circuit response data and to present the macro circuit response data at the K output pins of the macro circuit;
(e) transmitting the macro circuit response data from the K output pins of the macro circuit to the K MISR stages;
(f) using the MISR to process the macro circuit response data into a macro circuit response signature and send the macro circuit response signature to the K shift/interface circuits;
and
(g) scanning the macro circuit response signature out of the K shift/interface circuits in series.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/831,318Filed 31 Jul 2007 · division
Priority: 22 Feb 2005
Published: US 2008/0022171 A124 Jan 2008
Granted: 8 Jun 2010
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

G01R 31/318541
Using scanning techniques, e.g. LSSD, Boundary Scan, JTAG: scan latches or cell details
G01R 31/318519
Test of programmable logic devices [PLDs]: test of field programmable gate arrays [FPGA]
G01R
Measuring electric variables

Family

Application10/906,467Parent of this division · filed 22 Feb 2005
US 2008/0022171 A1Pre-grant publication · published 24 Jan 2008
US 7,308,630 B2Parent of this division
US 2006/0190782 A1Published application
US 7,734,968 B2This patent

From the US filing history. Foreign family members aren’t listed.