US 7,734,967 B2 · Semiconductor memory device and testing method of the same

Abstract

A semiconductor memory device, having a test mode and a normal mode, includes a frequency multiplier and a test command sequence generator. The frequency multiplier receives a test clock signal in the test mode and generates multiple internal test clock signals, each of which has a frequency equal to a frequency of an operation clock signal in the normal mode. The test clock signal has a frequency lower than the frequency of the operation clock signal. The test command sequence generator generates at least one command signal in response to the internal test clock signals in the test mode. The at least one command signal corresponds to at least one operation timing parameter of the semiconductor memory device that is to be measured. The frequency multiplier may include a Phase Locked Loop (PLL) or a Delay Locked Loop (DLL).

Claims12

Dependent claims

A semiconductor memory device having a test mode and a normal mode, the semiconductor memory device comprising:

a frequency multiplier that receives a test clock signal in the test mode and that generates first and second internal test clock signals, each having a frequency equal to a frequency of an operation clock signal in the normal mode, the test clock signal comprising a frequency lower than the frequency of the operation clock signal;
and
a test command sequence generator that generates at least one command signal in response to the first and second internal test clock signals in the test mode, the at least one command signal controlling at least one operation timing parameter of the semiconductor memory device that is to be measured,
wherein an initial point of the at least one operation timing parameter is controlled in response to the first internal test clock signal and an end point of the at least one operation timing parameter is controlled in response to the second internal test clock signal.

1 more element

A wafer level test method for a semiconductor memory device having a test mode and a normal mode, the method comprising:

applying a test clock signal having a frequency in the test mode lower than a frequency of an operation clock signal in the normal mode;
generating first and second internal test clock signals, each internal test clock signal having a frequency equal to the frequency of the operation clock signal;
generating command signals controlling operation timing parameters of the semiconductor memory device that are to be measured in response to the first and second internal test clock signals;
operating a memory core using the generated command signals and storing a test pattern in the memory core;
comparing a data pattern read from the memory core with the test pattern;
and
measuring the operation timing parameters of the semiconductor memory device based on the comparison of the data pattern read and the test pattern,
wherein an initial point of an operation timing parameter is controlled in response to the first internal test clock signal and an end point of the operation timing parameter is controlled in response to the second internal test clock signal.

5 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device and testing method of the same

Life of this patent

Semiconductor memory device and testing method of the same

Life of this patent

Abstract

Claims12