System and method for maintaining a constant processor service level in a computer

A method of recovering from a disabled processor event in a multiple processor computer system, the method comprising:

• detecting a disabled processor in a first module in a computer system comprising at least two modules;
• automatically attempting to enable a second processor in the first module to replace the disabled processor;
• attempting to enable a third processor in a second module to replace the disabled processor if the second processor does not respond;
• and
• increasing execution speed of processors other than the disabled processor to offset the loss of instruction execution from the disabled processor if the third processor does not respond.

A method of maintaining processor performance and recovering from a disabled processor in a computer system having at least two modules, each module containing at least two processors, the method comprising:

• (a) automatically detecting a change in instruction execution rate in a first processor, wherein the change varies more than a threshold amount;
• (b) determining an amount of change in instruction execution rate needed by one or more processors to adjust an actual system-level instruction execution rate to approximate a target system-level instruction execution rate;
• (c) automatically adjusting one or more instruction execution rates of the one or more processors such that the actual system-level instruction execution rate approximates the target system-level instruction execution rate;
• (d) automatically attempting to enable a second processor in a first module to replace the disabled processor;
• (e) attempting to enable a third processor in a second module to replace the disabled processor if the second processor does not respond;
• and
• (f) attempting to revive the disabled processor if the third processor does not respond;
• wherein steps (a), (b) and (c) are performed concurrently with steps (d), (e) and (f).

A system for maintaining execution rate in a computer system, the system comprising:

• at least two modules, each module having at least one processor;
• at least two processors, each processor having access to memory, the memory having commands which, when executed, perform the method comprising:
• automatically detecting a change in instruction execution rate in a first processor;
• determining an amount of change in instruction execution rate needed by one or more processors to adjust an actual system-level instruction execution rate to approximate a target system-level instruction execution rate;
• and
• automatically adjusting one or more instruction execution rates of the one or more processors such that the actual system-level instruction execution rate approximates the target system-level instruction execution rate;
• wherein the target system-level instruction execution rate comprises information found in a processor key.

A system for maintaining processor performance and recovering from a disabled processor in a computer system, the system comprising:

• at least two modules, each module having at least one processor;
• multiple processors, each processor having access to memory, the memory having commands which, when executed, perform the method comprising:
• (a) automatically detecting a change in instruction execution rate in a first processor, wherein the change varies more than a threshold amount;
• (b) determining an amount of change in instruction execution rate needed by the multiple processors to adjust a actual system-level instruction execution rate to approximate a target system-level instruction execution rate;
• (c) automatically adjusting one or more instruction execution rates of the multiple processors such that the actual system-level instruction execution rate approximates the target system-level instruction execution rate;
• (d) automatically attempting to enable a second processor in a first module to replace the disabled processor;
• (e) attempting to enable a third processor in a second module to replace the disabled processor if the second processor does not respond;
• and
• (f) attempting to revive the disabled processor if the third processor does not respond;
• wherein steps (a), (b) and (c) are performed concurrently with steps (d), (e) and (f).

A computer-readable medium having instructions therein, executable by a computer to perform a method of maintaining processor performance in a computer system having at least two processors, the method comprising:

• automatically detecting a change in instruction execution rate in a first processor, wherein the change varies more than a threshold amount;
• determining an amount of change in instruction execution rate needed by one or more processors to adjust an actual system-level instruction execution rate to approximate a target system-level instruction execution rate;
• and
• automatically adjusting one or more instruction execution rates of the one or more processors such that the actual system-level instruction execution rate approximates the target system-level instruction execution rate.

A computer-readable medium having instructions therein, executable by a computer to perform a method of recovering from a disabled processor in a computer system having at least two modules, each module containing at least two processors, the method comprising:

• (a) automatically detecting a change in instruction execution rate in a first processor, wherein the change varies more than a threshold amount;
• (b) determining an amount of change in instruction execution rate needed by one or more processors to adjust a actual system-level instruction execution rate to approximate a target system-level instruction execution rate;
• (c) automatically adjusting one or more instruction execution rates of the one or more processors such that the actual system-level instruction execution rate approximates the target system-level instruction execution rate;
• (d) automatically attempting to enable a second processor in the first module to replace the disabled processor;
• (e) attempting to enable a third processor in a second module to replace the disabled processor if the second processor does not respond;
• and
• (f) attempting to revive the disabled processor if the third processor does not respond;
• wherein steps (a), (b) and (c) are performed concurrently with steps (d), (e) and (f).