US 7,734,944 B2Granted

Mechanism for windaging of a double rate driver

AssigneeInternational Business Machines Corporation

InventorsJonathan Y. Chen, Jeffrey A. Magee, David A. Webber

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Abstract

A double data rate launch system and method in which the two-to-one multiplexer select signal delay is programmable and can be adjusted individually for each system. This allows the amount of delay to be minimized based on the actual set up time required, not the worst-case set-up time. The select signal to the multiplexer is delayed sufficiently to compensate for non-uniformity of duty cycle of data at the inputs to the multiplexer. Compensation of the non-uniformity allows the data on the wire to have a uniform duty cycle for all data transferred regardless of which latch is sourcing the data. The multiplexer that selects data from the two latches which are launching data on the edge of different clocks has a select line that is delayed by a variable amount to tune the select such that the data is clean at the input to the multiplexer on all ports.

Claims4

Dependent claims

A method for launching two bits of data from a chip on to one bus terminal at double the rate of the rate of and on-chip clock, including the steps of:

storing an even bit in an even bit master/slave register in response to a master m1/slave s1 clock signal operating at the on-chip clock rate;
storing and odd bit in an odd bit master/slave register in response to the master m1/slave s1 clock signal;
coupling an output of the even bit master/slave register as one input to a multiplexer whose output is coupled to said one bus terminal;
coupling an output of the odd bit master/slave register as an input to a master register that stores the input in response to a master m2 clock signal, and whose output is coupled as another input to said multiplexer, said master register delaying the output of the odd bit master/slave register for an interval determined by the master m2 clock signal;
coupling a select signal operating at said on-chip clock rate to said multiplexer to launch onto said bus terminal an even bit on one have cycle of said select signal and an odd bit on the other half cycle;
delaying said select signal with respect to the master m1/slave s1 clock signal and the master m2 clock signal with a delay element whose delay interval is programmable to match the signal set-up interval required by the inputs to said multiplexer;
and
determining the delay interval by comparing an edge of the select input to the multiplexer with an edge of a data bit on said bus terminal.

5 more elements

A system for launching two bits of data from a chip on to one bus terminal at double the rate of the rate of an on-chip clock, comprising in combination:

an even bit master/slave register that stores even bits in response to a master m1/slave1 clock signal operating at the on-chip clock cycle rate;
an odd bit master/slave register that stores odd bits in response to the master m1/slave s1 clock signal;
a multiplexer whose output is coupled to said one bus terminal has one of its inputs coupled to the slave output of the even master/slave register;
a master register coupled to an output of the odd bit master/slave register, said master register storing the output in response to a master m2 clock signal;
a select signal operating at said on-chip clock rate coupled to said multiplexer to launch onto said bus terminal an even bit on one half cycle of said select signal and an odd bit on the other half cycle;
a delay element delaying the select signal with respect to the master m1/slave s1 clock signal and the master m2 clock signal by a delay interval that is programmable to match the signal set-up time interval required by the inputs to said multiplexer;
a comparator for determining said delay interval by comparing an edge of the select input to the multiplexer with an edge of a data bit on said bus terminal.

4 more elements

Dependencies are inferred from the claim text.