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US 7,734,943 B2Granted
Low power display refresh
AssigneeIntel Corporation
InventorsRochelle J. Whelan, Marcus Grindstaff
Life of this patent
Estimating the term…
Abstract
An application processor coupled to a Static Random Access Memory (SRAM) interfaces with a graphics accelerator. A Dynamic Random Access Memory (DRAM) stores frame buffer data that may be transferred to a display through a switch located on the graphics accelerator in normal operation. In a power savings mode, the DRAM may be powered down and a copied frame buffer data stored in the SRAM may be transferred to the display through the switch.
Claims8
A method comprising:
- using a first display driver coupled to a graphics accelerator operating in a normal mode to supply frame buffer data from an external memory to a display;
- copying the frame buffer data stored in the external memory to a memory embedded with a processor;
- powering down the external memory and the first display driver in a power savings mode;
- and
- refreshing the display using a second display driver to supply the copied frame buffer data stored in the memory embedded with the processor.
2 more elements
A method for displaying data, comprising:
- fetching frame buffer data by a processor from a Dynamic Random Access Memory (DRAM) and a first display driver is used to provide a display with the fetched frame buffer data in normal operation;
- copying the frame buffer data stored in the DRAM to an SRAM embedded with the processor;
- and
- refreshing the display using a second display driver that receives the copied frame buffer data stored in the SRAM embedded with the processor.
1 more element
Dependencies are inferred from the claim text.