System and method for preventing an operating-system scheduler crash

A method for preventing an operating-system scheduler in a computer system from crashing as a result of an uncleared periodic interrupt, comprising the steps of:

• generating a periodic interrupt with a real-time clock (RTC) residing on a complementary metal-oxide semiconductor (CMOS) chip;
• checking a status register associated with the RTC in firmware residing on a chipset to determine whether a periodic interrupt is pending;
• entering the periodic interrupt into the status register associated with the RTC in the firmware residing on the CMOS chip, if the status register indicates no periodic interrupt has been pending;
• attempting to handle the periodic interrupt using an interrupt handler associated with the RTC;
• loading an inactivity timer with a stored value representing a preset interval of time;
• generating a system-management interrupt (SMI) using a basic-input-output system residing on a memory unit coupled to the CMOS chip, if the periodic interrupt is pending after the preset interval of time elapses;
• clearing any pending periodic interrupts from the status register with a firmware SMI handler residing on the memory unit, if the periodic interrupt is pending after the preset interval of time elapses;
• and
• updating a scheduler timer associated with the operating system once the status register has been cleared.

A system for preventing an operating-system scheduler in a computer system from crashing as a result of an uncleared periodic interrupt, comprising:

• a central processing unit;
• a chipset coupled to the central processing unit, wherein the chipset is programmed to generate a system management interrupt (SMI) if a periodic interrupt has not been cleared from a status register located on the chipset within a specified period of time;
• at least one firmware memory unit containing a Basic Input Output System (BIOS) coupled to the chipset, wherein the BIOS includes a SMI handler, wherein the SMI handler is programmed to clear any pending periodic interrupts from the status register if the periodic interrupt is pending after the specified period of time;
• and
• a memory unit coupled to the chipset and the central processing unit, wherein an operating system containing a scheduler and an interrupt handler is stored on the memory unit, and wherein the scheduler can access the status register.