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AssigneeElectronics and Telecommunications Research Institute
InventorsYoung Woo Kim, Sung Nam Kim, Kyoung Park, Seong Woon Kim, Myung Joon Kim
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Provided are a microprocessor suitable for constructing a multi-processor system and a method for controlling the reset and processor ID of the microprocessor. The microprocessor includes decoder receiving a reset ID having a predetermined binary value and a reset signal and decoding the reset ID, an ID generator receiving the decoding result of the decoder and generating at least one microprocessor ID and a reset ID of a microprocessor serially connected to the microprocessor, and a reset vector unit selecting a reset vector according to the decoding result of the decoder. The multi-processor system is constructed such that independent microprocessors of the system respectively generate their own reset vectors and processor IDs when a reset signal is input to the multi-processor system to initialize it. Thus, all the microprocessors of the system can be simultaneously started up when the reset signal is disabled. Accordingly, a resetting process in the multi-processor system is simplified, a period of time required for starting up the microprocessor is reduced, and the multi-processor system is easily designed.
A microprocessor suitable for constructing a multi-processor system, the microprocessor comprising:
A method for controlling a reset ID and processor ID of a microprocessor suitable for constructing a multi-processor system, the method comprising:
A computer readable recording medium storing a program executing in a computer a method of for controlling a reset ID and processor ID of a microprocessor suitable for constructing a multi-processor system, the method comprising:
Dependencies are inferred from the claim text.