Computer configuration virtual topology discovery and instruction therefore
AssigneeInternational Business Machines Corporation
InventorsMark S. Farrell, Charles W. Gainey, Jr., Jeffrey P. Kubala, Donald W. Schmidt
Life of this patent
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Abstract
In a logically partitioned host computer system comprising host processors (host CPUs), a facility and instruction for discovering topology of one or more guest processors (guest CPUs) of a guest configuration comprises a guest processor of the guest configuration fetching and executing a STORE SYSTEM INFORMATION instruction that obtains topology information of the computer configuration. The topology information comprising nesting information of processors of the configuration and the degree of dedication a host processor provides to a corresponding guest processor. The information is preferably stored in a single table in memory.
Claims24
In a logically partitioned host computer system comprising host processors (host CPUs), a method for a discovering topology of one or more guest processors (guest CPUs) of a guest configuration, the method comprising:
- a guest processor of the guest configuration fetching a STORE SYSTEM INFORMATION instruction for execution, the STORE SYSTEM INFORMATION instruction defined for a computer architecture;
- executing the STORE SYSTEM INFORMATION instruction comprising:
- based on a topology information request of the STORE SYSTEM INFORMATION instruction, obtaining topology information of the computer configuration the topology information comprising nesting information of processors of the configuration;
- and
- storing the topology information in a configuration topology table.
A computer program product for a discovering topology of one or more guest processors (guest CPUs) of a guest configuration in a logically partitioned host computer system comprising host processors (host CPUs), the computer program product comprising a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
- a guest processor of the guest configuration fetching a STORE SYSTEM INFORMATION instruction for execution, the STORE SYSTEM INFORMATION instruction defined for a computer architecture;
- executing the STORE SYSTEM INFORMATION instruction comprising:
- based on a topology information request of the STORE SYSTEM INFORMATION instruction, obtaining topology information of the computer configuration the topology information comprising nesting information of processors of the configuration;
- and
- storing the topology information in a configuration topology table.
A computer system comprising:
- a memory;
- a logically partitioned host computer system comprising host processors (host CPUs) in communication with said memory;
- wherein the computer system is configured to perform a method for a discovering topology of one or more guest processors (guest CPUs) of a guest configuration, the method comprising:
- a guest processor of the guest configuration fetching a STORE SYSTEM INFORMATION instruction for execution, the store system information instruction defined for a computer architecture;
- executing the STORE SYSTEM INFORMATION instruction comprising:
- based on a topology information request of the STORE SYSTEM INFORMATION instruction, obtaining topology information of the computer configuration the topology information comprising nesting information of processors of the configuration;
- and
- storing the topology information in a configuration topology table.
Dependencies are inferred from the claim text.