Reducing data hazards in pipelined processors to provide high processor utilization
AssigneeMicron Technology, Inc.
InventorsNeal Andrew Crook, Alan T. Wootton, James Peterson
Life of this patent
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Abstract
A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of instructions to operate concurrently on multiple pieces of data in multiple passes. One subset of instructions operates on one piece of data while different subsets of instructions operate concurrently on different pieces of data. A validity pipeline tracks the priming and draining of the pipeline processor to ensure that only valid data is written to registers or memory. Pass-dependent addressing is provided to correctly address registers and memory for different pieces of data.
Claims18
A method of operating a pipelined computer processor, said method comprising:
- i. identifying program instructions dependent upon results of prior program instructions in a set of instructions;
- ii. dividing said set of instructions into a plurality of subsets of instructions, each subset comprising a number of instructions from said set of instructions, based on the identified program instructions, each instruction of said set belonging to only one subset;
- iii. providing a validity pipeline comprising a first and a second stage where said first stage corresponds to a first of said subsets of instructions and said second stage corresponds to a second of said subsets of instructions;
- iv. assigning a bit indicating validity in said first stage when said first subset of instructions operating on a first piece of input data is processed to produce a first processed piece of input data;
- and
- v. propagating said bit in said first stage to said second stage when said second subset of instructions operating on said first processed piece of input data is processed.
A system for operating a pipelined computer processor, said system comprising:
- vi. a processor pipeline that identifies program instructions dependent upon results of prior program instructions in a set of instructions;
- vii. said processor pipeline that divides said set of instructions into a plurality of subsets of instructions, each subset comprising a number of instructions from said set of instructions, based on the identified program instructions, each instruction of said set belonging to only one subset;
- viii. a validity pipeline coupled to said processor pipeline comprising a first and a second stage where said first stage corresponds to a first of said subsets of instructions and said second stage corresponds to a second of said subsets of instructions;
- ix. said validity pipeline assigns a bit indicating validity in said first stage when said first subset of instructions operating on a first piece of input data is processed to produce a first processed piece of input data;
- and
- x. said validity pipeline propagates said bit in said first stage to said second stage when said second subset of instructions operating on said first processed piece of input data is processed.
An apparatus for operating a pipelined computer processor, said apparatus comprising:
- xi. means for identifying program instructions dependent upon results of prior program instructions in a set of instructions;
- xii. means for dividing said set of instructions into a plurality of subsets of instructions, each subset comprising a number of instructions from said set of instructions, based on the identified program instructions, each instruction of said set belonging to only one subset;
- xiii. a validity pipeline means comprising a first and a second stage where said first stage corresponds to a first of said subsets of instructions and said second stage corresponds to a second of said subsets of instructions;
- xiv. means for assigning a bit indicating validity in said first stage when said first subset of instructions operating on a first piece of input data means is processed to produce a first processed piece of input data means;
- and
- xv. means for propagating said bit in said first stage to said second stage when said second subset of instructions operating on said first processed piece of input data means is processed.
Dependencies are inferred from the claim text.