Enhanced processor element structure in a reconfigurable integrated circuit device
AssigneeFujitsu Microelectronics Limited
InventorHiroshi Furukawa
Life of this patent
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Abstract
A reconfigurable integrated circuit device which converts an arbitrary calculation state dynamically, based on configuration data, includes a plurality of processor elements, each of which has an input terminal, an output terminal, a plurality of arithmetic units which are provided in parallel and each of which performs calculation processing in synchronous with a clock signal, and an intra-processor network which connects them in an arbitrary state; and an inter-processor network which connects between processor elements in an arbitrary state. Based on configuration data, the intra-processor network is reconfigurable to a desired connection state, and further, based on the configuration data, the inter-processor network is reconfigurable to a desired connection state.
Claims8
A reconfigurable integrated circuit device which converts an arbitrary calculation state dynamically, based on configuration data, comprising:
- a plurality of processor elements, each of which comprises a plurality of input terminals, an output terminal, a plurality of arithmetic units which are provided in parallel and each of which performs calculation processing in synchronous with a clock signal, and an intra-processor element network which connects together said input terminals, and input and output ports of said plurality of arithmetic units in an arbitrary state;
- and
- an inter-processor element network which connects between said plurality of processor elements in an arbitrary state, wherein:
- said intra-processor element network has a plurality of first selectors, provided corresponding to all of the input ports of said plurality of arithmetic units, each of which has inputs connected to all of the input terminals and directly connected to all of the output ports of said arithmetic units, and an output connected to the corresponding input port of the arithmetic unit,
- said intra-processor element network further has a second selector having inputs connected to all of the output ports of the arithmetic units and an output connected to the output terminal,
- said intra-processor element network is reconfigurable to a desired connection state based on configuration data provided to the first selectors and the second selector, and further, said inter-processor element network is reconfigurable to a desired connection state based on said configuration data.
A reconfigurable integrated circuit device which converts an arbitrary calculation state dynamically, based on configuration data, comprising:
- a plurality of processor elements, each of which comprises a plurality of input terminals, an output terminal, a plurality of arithmetic units which are provided in parallel and each of which performs calculation processing in synchronous with a clock signal, and an intra-processor element network which connects together said input terminals, and input and output ports of said plurality of arithmetic units in an arbitrary state;
- an inter-processor element network which connects between said plurality of processor elements in an arbitrary state;
- and
- a control unit which supplies configuration data to said intra-processor element network and to said inter-processor element network;
- wherein
- said intra-processor element network has a plurality of first selectors, provided corresponding to all of the input ports of said plurality of arithmetic units, each of which has inputs connected to all of the input terminals and directly connected to all of the output ports of said arithmetic units, and an output connected to the corresponding input port of the arithmetic unit,
- said intra-processor element network further has a second selector having inputs connected to all of the output ports of the arithmetic units and an output connected to the output terminal,
- said intra-processor element network can be reconfigured to a desired connection state based on configuration data provided to the input selectors and the output selector, and further, said inter-processor element network can be reconfigured to a desired connection state based on said configuration data;
- and
- wherein each of said arithmetic units outputs its calculation processing result at a latency of one clock cycle.
A reconfigurable integrated circuit device which converts an arbitrary calculation state dynamically, based on configuration data, comprising:
- a plurality of processor elements, each of which comprises a plurality of input terminals, an output terminal, a plurality of arithmetic units which are provided in parallel and each of which performs calculation processing in synchronous with a clock signal, and an intra-processor element network which connects together said input terminals, and input and output ports of said plurality of arithmetic units in an arbitrary state;
- and
- an inter-processor element network which connects between said plurality of processor elements in an arbitrary state, wherein:
- said intra-processor element network has a plurality of first selectors, provided corresponding to all of the input ports of said plurality of arithmetic units, each of which has inputs connected to all of the input terminals and all of the output ports of said arithmetic units, and an output connected to the corresponding input port of the arithmetic unit, and which selects a signal among the all of the input terminals and all of the output ports of said arithmetic units so as to output the selected signal to said output,
- said intra-processor element network further has a second selector having inputs connected to all of the output ports of the arithmetic units and an output connected to the output terminal,
- said intra-processor element network is reconfigurable to a desired connection state based on configuration data provided to the first selectors and the second selector, and further, said inter-processor element network is reconfigurable to a desired connection state based on said configuration data.
Dependencies are inferred from the claim text.