Caching of microcode emulation memory

#1. Field of the Invention

#This invention relates to microprocessors and, more particularly, to emulation of complex instructions by microcode, and still more particularly, to caching of memory used during such emulation.

#2. Description of the Related Art

#FIG. 1 is a generalized block diagram of one embodiment of a computer system.

#FIG. 2 illustrates one embodiment of a virtual memory and cache architecture.

#FIG. 3 illustrates one embodiment of a process for accessing a memory hierarchy including microcode emulation memory.

#While the invention is susceptible to various modifications and alternative forms, specific embodiments are shown by way of example in the drawings and are herein described in detail. It should be understood, however, that drawings and detailed descriptions thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the invention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.

#FIG. 1 is a generalized block diagram of one embodiment of a computer system 100. In the illustrated embodiment, processor 110 is shown coupled to a memory 150. Memory 150 may include SDRAM, SRAM, ROM, DRAM and/or other conventional memory devices. Processor 110 includes a core 120, an L2 data cache 130, and an L2 translation lookaside buffer (TLB) 140. Core 120 includes an execution unit 122, a load/store unit 124, an L1 data cache 126, and an L1 TLB 128. L2 data cache 130 includes a microcode emulation memory 135. In alternative embodiments, processor 110 may include more than one core, each core including a level-1 data cache and each core sharing a single level-2 data cache. In one alternative embodiment, L1 data cache 126 may be separate from core 120. In other alternative embodiments, additional cache levels may be included in computer system 100, such as a level-3 cache, either included in processor 110 or separate from processor 110. In these and other alternative embodiments, microcode emulation memory 135 may be included in any cache level above level-1. A variety of other embodiments are also contemplated. However, for ease of understanding, the examples that follow will assume that space is permanently allocated in a level-2 data cache for microcode emulation memory 135.

#During operation, execution unit 122 may receive the data portion of loads to be executed from load/store unit 124 via link 161 and convey the data portion of stores to load/store unit 124 via link 162. Load/store unit 124 may receive the data portion of loads to be executed from L1 data cache 126 via link 163 and convey the data portion of stores to L1 data cache 126 via link 164. L1 data cache 126 may receive the data portion of loads from L2 data cache 130 via link 165 and convey the data portion of stores to L2 data cache 130 via link 166. L2 data cache 130 may receive the data portion of loads from and convey the data portion of stores to memory 150 via link 167. L1 TLB 128 is shown coupled to L1 data cache 126 via link 171, to L2 data cache 130 via link 172, and to L2 TLB 140 via link 173. L2 TLB 140 is also shown coupled to L2 data cache 130 via link 174.