Signal processor
AssigneeCasio Computer Co., Ltd.
InventorGoro Sakata
Life of this patent
Estimating the term…
Abstract
For every sampling period of a DSP 100, a timing generator 200 requests a CPU 300 to release a bus and provides a DSP 100 access time period to make an external memory 400 access the DSP 100 by occupying the bus released according to the request. In the DSP 100, during the DSP access time period, a memory interface section 11 executes read/write processing in which waveform data read from the external memory 400 is stored in an internal memory 12 and waveform data read from the internal memory 12 is written into the external memory 400 according to the command stored in an access command memory 10. At the same time, an operation section 13 executes operation processing by using the waveform data stored in the internal memory 12 independently of the read/write processing.
Claims3
A signal processor which includes a first operation processor and a second operation processor sharing an external memory via a bus, the signal processor comprising:
- an access time period setting section which requests a bus release to the second operation processor and sets an access time period by occupying the bus released from the second operation processor according to the request for every sampling period of the first operation processor;
- wherein the first operation processor executes read/write processing in relation to the external memory during the access time period set by the access time period setting section for every sampling period;
- and
- wherein the access time period setting section comprises:
- an access time period start direction section which generates a request signal requesting bus release and outputs the request signal to the second operation processor every time that a given time elapses from a start of the sampling period of the first operation processor, and which generates a start signal representing a start of the access time period and outputs the start signal to the first operation processor after waiting a given time from when the request signal was generated;
- and
- an access time period end direction section which ends the access time period by directing the access time period start direction section to stop the request signal and the start signal, in accordance with a completion signal generated when the first operation processor completes accessing the external memory.
Dependencies are inferred from the claim text.