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US 7,734,857 B2Granted
Cache coherent switch device
AssigneeIntel Corporation
InventorRamakrishna Saripalli
Life of this patent
Estimating the term…
Abstract
In one embodiment, the present invention includes a switch device to be coupled between a first semiconductor component and a processor node by interconnects of a communication protocol that provides for cache coherent transactions and non-cache coherent transactions. The switch device includes logic to handle cache coherent transactions from the first semiconductor component to the processor node, while the first semiconductor component does not include such logic. Other embodiments are described and claimed.
Claims18
An apparatus comprising:
- a switch device to be coupled between a first peripheral device and a processor node, the switch device to be coupled to the first peripheral device by a first interconnect of a first communication protocol and to the processor node by a second interconnect of the first communication protocol, where the first communication protocol provides for cache coherent transactions and non-cache coherent transactions, the switch device including first logic to handle cache coherent transactions from the first peripheral device to the processor node, wherein the first peripheral device is of an independent hardware vendor and does not include cache coherency logic to handle cache coherent transactions.
A method comprising:
- receiving in a switch, from a first peripheral device coupled to the switch by a first point-to-point (PtP) interconnect, a transaction directed to a processor coupled to the switch by a second PtP interconnect;
- determining in the switch if the transaction is a cache coherent transaction and if so, storing the transaction in a buffer of the switch and performing coherent-related transactions related to the cache coherent transaction including snooping cache transactions of the processor and invalidating a location in a cache of the processor corresponding to the cache coherent transaction if the cache coherent transaction is destined for the location, wherein the first and second PtP interconnects are of a first communication protocol and the switch and the first peripheral device are native devices of the first communication protocol, and the second semiconductor device is of an independent hardware vendor and does not include cache coherency logic to perform the coherent-related transactions;
- and
- after handling responses to the coherent-related transactions in the switch, forwarding the transaction from the buffer of the switch to the processor.
1 more element
A system comprising:
- a first processor node to perform operations on data;
- a first peripheral device including non-coherent logic to handle non-coherent transactions and first logic to issue cache coherent transactions but not to handle the cache coherent transactions;
- a switch device coupled to the first peripheral device by a first interconnect of a first communication protocol and to the first processor node by a second interconnect of the first communication protocol, where the first communication protocol provides for cache coherent transactions and non-cache coherent transactions, the switch device including second logic to handle the cache coherent transactions from the first peripheral device to the first processor node;
- a second processor node to perform operations on data;
- and
- a chipset coupled to the second processor node by a third interconnect of the first communication protocol.
3 more elements
Dependencies are inferred from the claim text.