Inter-processor communication link with manageability port

A microprocessor system, comprising:

• a processor core;
• at least one processor subsystem to communicate with the processor core using at least one microprocessor bus;
• a communication link connected to at least an inter-processor bus to enable inter-processor communication, the communication link to provide a multi-channel inbound link and a multi-channel outbound link, and to control data flow over a plurality of channels for both the multi-channel inbound and outbound links,
• the multi-channel inbound link providing a path for communications from the inter-processor bus to a peripheral bus of the microprocessor system, the multi-channel inbound link receiving communications from at least one processor or peripheral communicating over the inter-processor bus, and
• the multi-channel outbound link providing a path for communications from the peripheral bus of the microprocessor system to the inter-processor bus, the multi-channel outbound link transmitting communications over the inter-processor bus to the at least one processor or peripheral;
• and
• a management block to receive command data from the at least one processor or peripheral using a predetermined logic channel in the multi-channel inbound link, the management block providing a corresponding command signal on the at least one microprocessor bus, which relays the command signal to at least one processor or peripheral of the microprocessor system, the command signal performing a management function for at least one of the processor core and the at least one processor subsystem, the management block being further adapted to receive a response signal from the microprocessor bus and the management block transmitting corresponding response data through a predetermined logic channel in the outbound link to the at least one processor or peripheral via the inter-processor bus, the management block including a manageability control module,
• the manageability control module configured to apply a protocol for communicating over the microprocessor bus, and
• the manageability control module configured to provide access for allowing another microprocessor system to perform the management function even when the processor core is not responsive to any signal.

A microprocessor system for a wireless device, comprising:

• a processor core and at least one processor subsystem;
• at least one bus to connect the processor core to the at least one processor subsystem;
• means for providing a multi-channel inbound link and a multi-channel outbound link, connected to at least an inter-processor bus for inter-processor communication in the wireless device, and to control data flow over a plurality of channels for both the multi-channel inbound and outbound links;
• the multi-channel inbound link providing a path for communications from the inter-processor bus to a peripheral bus of the microprocessor system, the multi-channel inbound link receiving communications from at least one processor or peripheral communicating over the inter-processor bus, and
• the multi-channel outbound link providing a path for communications from the peripheral bus of the microprocessor system to the inter-processor bus, the multi-channel outbound link transmitting communications over the inter-processor bus to the at least one processor or peripheral;
• and
• means for receiving command data from the at least one processor or peripheral through a predetermined logic channel in the inbound link, the means for receiving command data providing a corresponding command signal on the bus with an appropriate communication protocol to perform a management function for at least one processor subsystem, the bus relaying the command signal to at least one processor or peripheral of the microprocessor system;
• means for providing access for allowing another microprocessor system to perform the management function even when the processor core is not responsive to any signal;
• and
• means for receiving a response signal from the bus and transmitting corresponding response data through a predetermined logic channel in the outbound link to the at least one processor or peripheral via the inter-processor bus.

A system, comprising:

• an embedded applications microprocessor system and an embedded communications microprocessor system, each microprocessor system including a communication link to enable inter-processor communication over multiple channels;
• a substantially omni-directional antenna connected to the embedded communications microprocessor system;
• an inter-processor communication bus connected to the communication links of both the applications microprocessor system and the communications microprocessor system;
• and
• the communication link of the applications microprocessor system being connected to at least an inter-processor bus, and including:
• a multi-channel inbound link and a multi-channel outbound link, the communications link being adapted to control data flow over the multi-channel inbound and outbound links,
• the multi-channel inbound link providing a path for communications from the inter-processor bus to a peripheral bus of the microprocessor system, the multi-channel inbound link receiving communications from at least one processor or peripheral communicating over the inter-processor bus, and
• the multi-channel outbound link providing a path for communications from the peripheral bus of the microprocessor system to the inter-processor bus, the multi-channel outbound link transmitting communications over the inter-processor bus to the at least one processor or peripheral;
• and
• a manageability port to allow the communications microprocessor system to access a microprocessor bus local to the applications microprocessor system using at least one predetermined channel and to perform management functions in the applications microprocessor system, the manageability port:
• being adapted to receive command data from the at least one processor or peripheral through a predetermined logic channel in the inbound link, applying a protocol for communicating over the microprocessor bus, providing a corresponding command signal on the microprocessor bus, which relays the command signal to at least one processor or peripheral of the applications microprocessor system, and further is adapted to receive a response signal from the microprocessor bus,
• providing access for allowing the communications microprocessor system to perform management functions even when a processor core of the applications microprocessor system is not responsive to any signal, and
• transmitting corresponding response data through a predetermined logic channel in the outbound link to the at least one processor or peripheral communicating over the inter-processor bus.

A method, comprising:

• receiving an inter-processor communication signal at a communications link for a microprocessor system, the communication link connected at least to an inter-processor bus, and used to provide a multi-channel inbound link and a multi-channel outbound link for the microprocessor system, and to control inter-processor data flow over the multi-channel inbound and outbound links, wherein receiving an inter-processor communication signal includes receiving a signal using a predetermined channel of the multi-channel inbound link, the signal including command data to perform a management function for a microprocessor subsystem,
• the multi-channel inbound link providing a path for communications from the inter-processor bus to a peripheral bus of the microprocessor system, the multi-channel inbound link receiving communications from at least one processor or peripheral communicating over the inter-processor bus,
• the multi-channel outbound link providing a path for communications from the peripheral bus of the microprocessor system to the inter-processor bus, the multi-channel outbound link transmitting communications over the inter-processor bus to the at least one processor or peripheral;
• processing the command data by a management block to generate and transmit a corresponding command signal on a microprocessor bus, which relays the command signal to at least one processor or peripheral of the microprocessor subsystem, the microprocessor bus local to the microprocessor system using an appropriate bus communication protocol to perform the management function;
• and
• providing access by a management control block of the management block for allowing another microprocessor system to perform the management function even when a processor core of the microprocessor system is not responsive to any signal.