System and method for generating a binary result in a data processing environment

A method for processing data comprising:

• generating one or more binary results based on one or more inputs at a plurality of logic elements by:
• generating, by a NAND gate of the logic elements, a generate-bar output from the inputs;
• and
• generating, by a NOR gate of the logic elements, a kill output from the inputs;
• generating, by a propagate cell, one or more conditional carryout signals, without using inverters, in a single stage based on one or more of the binary results and a carry-in signal, the propagate cell coupled to one or more of the logic elements that are non-complementary, the generating the conditional carryout signals comprising:
• yielding a carryout output of zero if the generate-bar output is one and the kill output is one;
• yielding a carryout output of one if the generate-bar output is one, the kill output is zero, and the carry-in signal is one without inverting the carry-in signal input to the propagate cell;
• yielding a carryout output of zero if the generate-bar output is one and the kill output is zero, and the carry-in signal is zero without inverting the carry-in signal input to the propagate cell;
• and
• yielding a carryout output of one if the generate-bar output is zero and the kill output is zero;
• generating one or more carryout signals that are based on one or more of the conditional carryout signals;
• generating, by a multiplexer, a sum based on the carryout signals;
• and
• communicating the sum to an adder circuit, and whereby a plurality of additional propagate cells are provided in parallel processing sections that receive the conditional carryout signals.

A system for processing data comprising:

• means for generating one or more binary results based on one or more inputs at a plurality of logic elements by:
• generating, by a NAND gate of the logic elements, a generate-bar output from the inputs;
• and
• generating, by a NOR gate of the logic elements, a kill output from the inputs;
• means for generating, by a propagate cell, one or more conditional carryout signals, without using inverters, based on one or more of the binary results and a carry-in signal, the propagate cell coupled to one or more of the logic elements that are non-complementary, the generating the conditional carryout signals comprising:
• yielding a carryout output of zero if the generate-bar output is one and the kill output is one;
• yielding a carryout output of one if the generate-bar output is one, the kill output is zero, and the carry-in signal is one without inverting the carry-in signal input to the propagate cell;
• yielding a carryout output of zero if the generate-bar output is one and the kill output is zero, and the carry-in signal is zero without inverting the carry-in signal input to the propagate cell;
• and
• yielding a carryout output of one if the generate-bar output is zero and the kill output is zero;
• means for generating one or more carryout signals that are based on the conditional carryout signals;
• means for generating, by a multiplexer, a sum based on the carryout signals;
• and
• communicating the sum to an adder circuit, and whereby a plurality of additional propagate cells are provided in parallel processing sections that receive the conditional carryout signals.

A computer readable storage medium having code for processing data and configured to interface with the code operable to:

• generate one or more binary results based on one or more inputs at a plurality of logic elements by:
• generating, by a NAND gate of the logic elements, a generate-bar output from the inputs;
• and
• generating, by a NOR gate of the logic elements, a kill output from the inputs;
• generate, by a propagate cell, one or more conditional carryout signals, without using inverters, in a single stage based on one or more of the binary results and a carry-in signal, the propagate cell coupled to one or more of the logic elements that are non-complementary, the generating the conditional carryout signals comprising:
• yielding a carryout output of zero if the generate-bar output is one and the kill output is one;
• yielding a carryout output of one if the generate-bar output is one, the kill output is zero, and the carry-in signal is one without inverting the carry-in signal input to the propagate cell;
• yielding a carryout output of zero if the generate-bar output is one and the kill output is zero, and the carry-in signal is zero without inverting the carry-in signal input to the propagate cell;
• and
• yielding a carryout output of one if the generate-bar output is zero and the kill output is zero;
• generate one or more carryout signals that are based on the conditional carryout signals;
• generate, by a multiplexer, a sum based on one or more of the carryout signals;
• and
• communicate the sum to an adder circuit, and whereby a plurality of additional propagate cells are provided in parallel processing sections that receive the conditional carryout signals.