Fast fourier transform (FFT) architecture in a multi-mode wireless processing system

A system for performing a Fast Fourier Transform (FFT) in a multi-mode wireless processing system, the system comprising:

• a processing unit for performing vector operations;
• a memory for providing mathematical functions to the processing unit;
• a program memory containing instructions for executing an FFT algorithm;
• an instruction controller for receiving and executing instructions from the program memory;
• a counter configured to store a value indicative of a current stage of the FFT algorithm, where s is a value of the second counter, and wherein the value of the counter is configured to be adjusted by a value greater than one in response to an indication that a stage of the FFT algorithm has completed an operation;
• and
• a pair of buffers that alternate between acting as an input buffer and an output buffer in successive FFT stages of the FFT algorithm, data in the input buffer comprising a plurality of segments.

A method, comprising:

• loading an input vector into an input buffer;
• initializing a counter and a variable N, where N=log.sub.2 (input vector size), and s is a value of the counter;
• performing an FFT stage, the FFT stage comprising:
• determining a first address based on a value of the counter;
• accessing data stored at the input buffer based on the first address;
• performing vector operations on the data in the input buffer and sending results to an output buffer;
• and
• advancing the value of the counter by a value greater than one;
• and
• comparing s to N, and performing additional FFT stages until s=N.