Method and system for performing ternary verification
AssigneeInternational Business Machines Corporation
InventorsJason R. Baumgartner, Hari Mony, Viresh Paruthi, Matyas A. Sustik
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Abstract
A method and system for performing ternary verification is disclosed. Initially, a ternary model is generated from a binary model of a logic circuit design. The pairings used to encode the ternary model are then recorded. Next, the number of the recorded gate pairings is reduced by removing all invalid gate pairings. A ternary verification is performed on the ternary model having a reduced number of gate pairings.
Claims12
A computer implemented method for performing ternary verification, said method comprising:
- generating a ternary model from a binary model of an integrated logic circuit design, wherein said ternary model includes a logic 0 valuation, a logic 1 valuation, and an X valuation for representing an unknown condition;
- recording gate pairings used to encode said ternary model;
- reducing the number of said recorded gate pairings by removing invalid gate pairings;
- performing ternary verification on said ternary model having a reduced number of gate pairings;
- and
- generating by a computer a result of said ternary verification.
A computer usable medium having a computer program product for performing ternary verification, said computer usable medium comprising:
- computer program code for generating a ternary model from a binary model of a logic circuit design, wherein said ternary model includes a logic 0 valuation, a logic 1 valuation, and an X valuation for representing an unknown condition;
- computer program code for recording gate pairings used to encode said ternary model;
- computer program code for reducing the number of said recorded gate pairings by removing invalid gate pairings;
- computer program code for performing ternary verification on said ternary model having a reduced number of gate pairings;
- and
- computer program code for generating a result of said ternary verification.
A computer system for performing ternary verification, said computer system comprising:
- means for generating a ternary model from a binary model of a logic circuit design, wherein said ternary model includes a logic 0 valuation, a logic 1 valuation, and an X valuation for representing an unknown condition;
- means for recording gate pairings used to encode said ternary model;
- means for reducing the number of said recorded gate pairings by removing invalid gate pairings;
- and
- means for performing ternary verification on said ternary model having a reduced number of gate pairings.
Dependencies are inferred from the claim text.