System and method for de-scrambling and bit-order-reversing payload bytes in an Asynchronous Transfer Mode cell
AssigneeBroadcom Corporation
InventorsMark Taunton, Timothy Martin Dobson
Life of this patent
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Abstract
A method and apparatus are disclosed for efficiently de-scrambling and bit-order-reversing one or more bytes of data according to DSL standards on a processor. In a preferred embodiment, this is achieved by providing an instruction for de-scrambling and bit-order-reversing one or more bytes of data according to DSL standards. Accordingly, the invention advantageously provides a processor with the ability to de-scramble and bit-order-reverse data with a single instruction thus allowing for more efficient and faster de-scrambling operations for subsequent processing.
Claims22
A method for executing a single instruction de-scrambler and bit-order-reversal on a processor, the method comprising:
- providing the processor with a single instruction that includes an opcode indicating a de-scrambling and bit-order-reversal instruction;
- providing the processor with an input data value using a first field of the instruction;
- providing the processor with an input state value using a second field of the instruction;
- providing the processor with a reference to a destination register of the processor using a third field of the instruction;
- de-scrambling and bit-order-reversing the input data value using the input state value to create a de-scrambled and bit-order-reversed output value;
- and
- storing the de-scrambled and bit-order-reversed output value in the destination register.
A processor comprising:
- a plurality of registers;
- and
- at least one execution unit, coupled to the plurality of registers, configured to receive a single bit-order-reversal and de-scrambling instruction that includes a first field relating to an input data value and second field relating to an input state value, de-scramble and bit-order-reverse the input data value using the input state value to generate a de-scrambled and bit-order-reversed output data value, and store said de-scrambled and bit-order-reversed output data value in at least one of said plurality of registers.
An apparatus comprising:
- a processor, responsive to a single instruction that includes a first field relating to an input data value and a second field relating to an input state value, comprising means for de-scrambling and bit-order-reversing said input data value using said input state value to generate a de-scrambled and bit-order-reversed output data value;
- a plurality of registers accessible to the processor, wherein said de-scrambled and bit-order-reversed output data value is stored in at least one of the plurality of registers.
Dependencies are inferred from the claim text.