Fractional frequency divider circuit and data transmission apparatus using the same

A data transmission apparatus comprising:

• a receiver circuit that performs serial-parallel conversion on a received signal and outputs the result;
• a transmitter circuit that performs parallel-serial conversion on a transmitted signal and outputs the result;
• a PLL that multiplies a reference clock signal and outputs a multiplied clock signal;
• and
• a fractional frequency divider circuit that outputs a signal obtained by frequency-dividing said multiplied clock signal with a frequency-division ratio of 2/N where N is an integer,
• wherein said fractional frequency divider circuit comprises an integer frequency divider circuit and a logic circuit, said integer frequency divider circuit comprising multiple master-slave flip flops connected in series and each of the master flip-flops in the multiple master-slave flip-flops receives a first clock signal and each of the slave flip-flops in the multiple master slave flip-flops receives a clock signal which is 180 degrees out of phase with the first clock signal,
• said integer frequency divider circuit frequency-dividing said multiplied clock signal with a frequency-division ratio of 1/N,
• said logic circuit receiving a plurality of signals output from master stages and slave stages of said multiple master-slave flip-flops, and said logic circuit comprising a first data latch which receives a clock signal which is 90 degrees out of phase with the multiplied clock signal and a second data latch which receives a clock signal which is 270 degrees out of phase with the multiplied clock signal, and outputting a signal obtained by frequency-dividing said multiplied clock signal with a frequency-division ratio of 2/N where N is an integer, and
• said receiver circuit and transmitter circuit being constituted such that they operate selectively switching over between said multiplied clock signal and a clock signal output by said fractional frequency divider circuit.