System and method for an adaptable timing recovery architecture for critically-timed transport applications

A method for providing timing recovery of a digital clock for a digital transmission comprising:

• providing a phase smoothing circuit, wherein the phase smoothing circuit redistributes timing discontinuities caused by the removal of overhead bytes, pointer justification bytes, stuff bytes, or other phase discontinuities in a signal, into a series of smaller and more frequent phase discontinuities in order to remove low frequency components in the power spectrum of the signal, and
• providing a clock gapping circuit, wherein the clock gapping circuit outputs a timing pulse train with an average frequency equal to a desired output clock frequency, and wherein the clock gapping circuit utilizes analog proportional/differential control with feedback, and
• wherein the timing pulse train is achieved by inhibiting timing pulses on a system clock based on a ratio that is proportional to an average output frequency relative to the system clock, and
• wherein a plurality of controlled clock gapping circuits are cascaded in a series, such that a highest gain control circuit is first in the series, followed by a one or more lower gain stages, and
• wherein a plurality of controlled clock gapping circuits are cascaded such that the system is a three-stage implementation, wherein stage 1 is a fast response filtering stage which performs the phase smoothing function, stage 2 is a low gain filtering stage which performs the timing recovery function, and stage 3 is a medium gain filtering stage further comprised of a final phase-locked loop (PLL) filter and a controlled oscillator placed at the end of the series of cascaded controlled clock gapping circuits.

A three-stage timing recovery, controlled clock gapping circuit apparatus, comprising:

• a first stage fast response filtering controlled clock gapping circuit, wherein the clock gapping circuit outputs a timing pulse train, a first gapped clock, with an average frequency equal to a desired output clock frequency,
• wherein the first stage delivers the first gapped clock to a second stage,
• a second stage filtering controlled clock gapping circuit, wherein the clock gapping circuit outputs a timing pulse train, a second gapped clock, with an average frequency equal to a desired output clock frequency,
• wherein the second stage implements a slow response to changes in the first gapped clock, generates the filtered, second gapped clock, and delivers the second gapped clock to a third stage,
• a third stage filtering circuit,
• wherein the third stage maintains a voltage controlled crystal oscillator locked to the second gapped clock received from the second stage,
• wherein the first and second gapped clocks are achieved by inhibiting timing pulses, gapping, on the system clock based on a ratio that is proportional to an average output frequency relative to the system clock, and
• wherein the controlled clock gapping circuits are cascaded in a series, and
• wherein the controlled clock gapping circuits utilize analog proportional/differential control with feedback.