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US 7,733,920 B1Granted
Programmable pre-emphasis circuit for serial ATA
AssigneeMarvell International Ltd.
InventorsLei Wu, Timothy Hu
Life of this patent
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Abstract
A high-speed serial ATA physical layer includes a serial ATA control circuit. A serial ATA multiplexer outputs one of a plurality of serial ATA signals that is selected by the serial ATA control circuit. A serial ATA analog front end provides a first gain and pre-emphasis to the selected one of the plurality of serial ATA signals. The pre-emphasis alters a transmission characteristic of the selected one of the plurality of serial ATA signals.
Claims18
A high-speed serial ATA physical layer comprising:
- a serial ATA control circuit;
- a serial ATA multiplexer that outputs one of a plurality of serial ATA signals,
- wherein said one of said plurality of serial ATA signals is selected by said serial ATA control circuit;
- and
- a serial ATA analog front end that provides a first gain and pre-emphasis to said selected one of said plurality of serial ATA signals,
- wherein said pre-emphasis alters a transmission characteristic of said selected one of said plurality of serial ATA signals.
3 more elements
A high-speed serial ATA physical layer comprising:
- a serial ATA control circuit;
- a serial ATA multiplexer that outputs one of a plurality of serial ATA signals,
- wherein said one of said plurality of serial ATA signals that is selected by said serial ATA control circuit;
- and
- a serial ATA analog front end that provides a first gain and pre-emphasis to said selected one of said plurality of serial ATA signals,
- wherein:
- said pre-emphasis alters a transmission characteristic of said selected one of said plurality of serial ATA signals;
- and
- said serial ATA analog front end includes:
- a first driver that generates a first amplified signal;
- and
- a pre-emphasis circuit that includes:
- a first delay element that delays said selected one of said plurality of serial ATA signals to generate a first delayed signal;
- a second driver that amplifies said first delayed signal using a second gain to generate a second amplified signal;
- and
- a first summing circuit that adds said first amplified signal and said second amplified signal to generate a sum.
13 more elements
A high-speed serial ATA physical layer comprising:
- a serial ATA control circuit;
- a serial ATA multiplexer that outputs one of a plurality of serial ATA signals,
- wherein said one of said plurality of serial ATA signals that is selected by said serial ATA control circuit;
- and
- a serial ATA analog front end that provides a first gain and pre-emphasis to said selected one of said plurality of serial ATA signals,
- wherein:
- said pre-emphasis alters a transmission characteristic of said selected one of said plurality of serial ATA signals;
- and
- said serial ATA analog front end includes a first driver that includes:
- a gain control circuit that controls said first gain;
- and
- n differential amplifiers comprising:
- differential inputs that communicate with first and second inputs;
- differential outputs that communicate with first and second outputs;
- and
- enable inputs that communicate with said gain control circuit,
- wherein said gain control circuit selectively enables said n differential amplifiers to adjust said first gain.
14 more elements
Dependencies are inferred from the claim text.