Forced bubble insertion scheme
AssigneeBroadcom Corporation
InventorsAnupam Anand, Chien-Hsien Wu, Samir K. Sanghani
Life of this patent
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Abstract
A network device for processing packets. The network device includes a memory management unit for storing packets and performing resource checks on each packet and an egress module for performing packet modification and transmitting the packet to a destination port. The memory management unit includes a timer for indicating that a free space should be created on a bus slot between the memory management unit and the egress module, wherein the free space is used for transmitting CPU instructions from the memory management unit to the egress module.
Claims18
A network device for processing packets, the network device comprising:
- a memory management unit configured to store packets and perform resource checks on each packet the memory management unit including a timer;
- and
- an egress module configured to perform packet modifications and transmit the packet to a destination port, and
- wherein the memory management unit is configured to:
- detect an expiration of the timer;
- create a non-natural free space or empty slot on a bus between the memory management unit and the egress module when the timer expires and after an end of cell of a packet;
- and
- transmit a CPU instruction from the memory management unit to the egress module on the created free space or empty slot on the bus.
A method for processing packets on a network device, the method comprising the steps of:
- initializing a timer in a memory management unit;
- creating a non-natural free space or empty slot on a bus between the memory management unit and an egress module when the timer expires and after an end of cell of packet;
- and
- transmitting one or more CPU instructions from the memory management unit to the egress module using the created free space.
An apparatus for processing packets in a network device, the apparatus comprising a memory management unit, the apparatus configured to:
- initialize a timer in a memory management unit;
- create a non-natural free space or empty slot on a bus between the memory management unit and an egress module when the timer expires and after an end of cell of packet;
- and
- transmit one or more CPU instructions from the memory management unit to the egress module using the created free space.
Dependencies are inferred from the claim text.