Synchronous semiconductor memory device
AssigneeHynix Semiconductor Inc.
InventorsKyoung-Nam Kim, Sang-Hee Kang
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Abstract
A synchronous semiconductor memory device of the present invention includes: an operation controller for outputting a column active sense pulse in response to a column address and a column command signal; a shift register controller, activated in response to the column active sense pulse, for dividing a clock signal by N to thereby output a divided clock signal, N being a positive integer greater than 1; a plurality of shift registers connected in series and synchronized with the divided clock signal, wherein each shift register transmits the column active sense pulse to the next shift register; and a column active control signal generator for logically combining outputs of the shift registers to thereby generate a column active control signal.
Claims19
A synchronous semiconductor memory device, comprising:
- a shift register controller, activated in response to a column active sense pulse generated based on a column address and a column command signal, for dividing a clock signal by N to thereby output a divided clock signal, N being a positive integer greater than 1;
- and
- a plurality of shift registers connected in series and synchronized with the divided clock signal, wherein each shift register transmits the column active sense pulse to the next shift register.
A synchronous semiconductor memory device, comprising:
- a control unit, activated in response to a column active sense pulse, for dividing an external clock signal by N to thereby output a divided clock signal, N being a positive integer greater than 1;
- and
- a plurality of shift registers connected in series and synchronized with the divided clock signal, wherein each shift register transmits the column active sense pulse to the next shift register.
Dependencies are inferred from the claim text.